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as3517 v17 data sheet, confidential data sheet, confidential as3517 stereo audio codec with enha nced system power management 1 general description the as3517 is a low power stereo audio codec and is designed for portable digital audio applications. it allows playback and recording in cd quality. it has a variety of audio inputs and outputs to directly connect electret microphones, 16 /32 headsets and auxiliary signal sources via a 10- channel mixer. it only consumes 20mw in playback mode. further the device offers advanced power management func tio ns. all necessary ics and peripherals in a digital audio player with flash or harddisk memory are supplied by the as3517. the different regulated supply voltages are programmable via the serial control interface. the power management block generates 11 different supply voltages out of a single battery supply. cpu, nand flash, sram, memory cards, harddisk, lcd, lcd backlight, usb-host and usb- otg can be powered. as3517 also contains a charger. the single supply voltage may vary from 3.0v to 5.5v. the as3517 has an on-chip, phase locked loop (pll) c ontrol led, clock generator. it generates 44.1khz, 48khz and other sample rates defined in mp3, aac, wma, ogg vorbis etc. no additional external crystal or pll is needed in slave mode. further the as3517 has an independent 32khz real time clock (rtc) on chip which allows a complete power down of the system cpu. 2 key features ? multi-bit sigma delta converters ? dac: 94db snr (?a? weighted) @ 2.9v ? adc: 90db snr (?a? weighted) @ 2.9v ? sampling frequency: 8-48khz ? 2 mic rophone inputs ? 3 gain pre-setting (28db/34db/40db) and agc ? 32 gain steps @1.5db and mute ? supply for electret microphone ? microphone detection ? remote control by switch ? 2 li ne inputs ? volume control via serial interface ? 32 steps @1.5db and mute ? stereo or 2x mono or mono differential ? audi o mixer ? 10 channel input/output mixer with agc ? mixes line inputs and microphones with dac ? left and right channels independent ? 2 li ne outputs ? volume control via serial interface ? 32 steps @1.5db and mute ? 1vp @10k ? stereo 2*5mw to 16ohm ? differential 10mw to 32ohm (earpiece) ? high ef ficiency headphone amplifier ? volume control via serial interface ? 32 steps @1.5db and mute ? 2x60mw @16 driver capability ? headphone and over-current detection ? phantom ground eliminates large capacitors ? power m anagement ? s tep down for cpu core (0.65v-3.4v, 250ma) ? step down for peripheral (0.65v-3.4v, 250ma) ? step down for harddisk (0.65v-3.4v, 500ma) ? step up for backlight (15v (25v), 38ma), ? ldo for digital supply (2.9v, 200ma) ? ldo for analog supply (2.9v, 200ma) ? ldo for peripherals (1.2v-3.5v, 200ma) ? ldo for peripherals (1.2v-3.5v, 200ma) ? ldo for rtc (1.0v-2.5v, 2ma) ? power supply supervision ? hibernation modes ? 5sec and 10sec emergency shut-down ? battery charger ? au tomatic trickle charge (50ma) ? prog. constant current charging (50-460ma) ? prog. constant voltage charging (3.9v-4.25v) ? real t ime clock ? ultr a low power 32khz oscillator ? 32bit rtc sec counter, 96 days auto wake-up ? selectable alarm (seconds or minutes) ? 128bit free sram for random settings ? 32khz clock output to peripheral ? aux iliary oscillator (only for master clock mode) ? low power 12-24mhz oscillator ? master clock input/output (e.g. from/to cpu) ? genera l purpose adc ? 10 bit resolution ? 21 inputs analog multiplexer ? interf aces ? i2s d igital audio interface and spdif ? 2 wire serial control interface ? reset pin, watchdog, power good pin ? pwm output ? 128bit unique id (otp) ? 30 different interrupts ? pac kage ctbga81 [9.0x9.0x1.15mm] 0.8mm pitch 3 application portable digital audio player and recorder pda, smartphone ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com revision 1v3 1 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 4 functional overview keys lcd controller de/encoder application processor flash sd- ram mmc, sd etc hd reset & wd rtc osc/pll i2s 2w interface drm id pmu = voltage supply + supply supervision + power-up + hibernation usb host / otg spdif out pwm out audio dac headphone amplifier line outputs audio adc microphone amplifier line inputs pmu = voltage supply + supply supervision + power-up + hibernation fm- radio dc/dcs - ldos charger 3v-5v battery 5v charger as3517 voltage supply digital interface audio signal revision 1v3 2 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 5 block diagram figure 1 as3517 block diagram revision 1v3 3 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com contents 1 general de scripti on ............................................................................................................ ............................. 1 2 key feat ures................................................................................................................... ................................. 1 3 applicat ion ....................................................................................................................................................... 1 4 functional overview ............................................................................................................ ............................ 2 5 block di agram .................................................................................................................................................. 3 6 pinout and packagi ng ........................................................................................................... ........................... 6 6.1 pin descr iption.......................................................................................................................................... 6 6.2 ball assi gnment ................................................................................................................ ........................ 8 6.2.1 ctbga81 ........................................................................................................................ .................. 8 6.3 package dr awings ............................................................................................................... ..................... 9 6.3.1 ctbga81 ........................................................................................................................ .................. 9 7 ordering in formati on ........................................................................................................... ........................... 10 8 absolute maximum rati ngs (non-op erating)....................................................................................... .......... 11 8.1 operating c onditio ns ........................................................................................................... ................... 12 8.1.1 supply voltages................................................................................................................ ............... 12 8.1.2 operating currents ............................................................................................................. ............. 13 8.1.3 temperatur e range.............................................................................................................. ........... 13 8.1.4 audio specif icatio n ............................................................................................................ .............. 14 9 detailed functiona l descrip tion ................................................................................................ ..................... 16 9.1 audio f unctions ................................................................................................................ ...................... 16 9.1.1 audio line in puts (2x)......................................................................................................... ............. 16 9.1.2 microphone i nputs (2 x) ......................................................................................................... ........... 18 9.1.3 audio line ou tputs (2x) ........................................................................................................ ........... 20 9.1.4 headphone out put ............................................................................................................... ........... 21 9.1.5 dac, adc and i2s digital audio inte rface ...................................................................................... 2 3 9.1.6 audio output mixer ............................................................................................................. ............. 28 9.1.7 2-wire-serial cont rol inte rface ................................................................................................ ........ 29 9.2 power management functi ons ..................................................................................................... .......... 32 9.2.1 low drop out regula tors ........................................................................................................ ........ 32 9.2.2 dcdc step-down c onverter (3x).................................................................................................. .. 35 9.2.3 char ger........................................................................................................................ .................... 39 9.2.4 15v step-up conver ter .......................................................................................................... ......... 41 9.2.5 usb vbus supply................................................................................................................ ........... 43 9.3 system f uncti ons ............................................................................................................... ................. 46 9.3.1 system......................................................................................................................... ................. 46 9.3.2 hibernat ion .................................................................................................................... .................. 49 9.3.3 supervi sor ..................................................................................................................... .................. 50 9.3.4 interrupt g eneratio n........................................................................................................... .............. 51 9.3.5 real time clock ................................................................................................................ .............. 52 9.3.6 10-bit adc..................................................................................................................... .................. 53 9.3.7 unique id code ( 64 bit ot p rom) ................................................................................................ .54 9.4 register de scription ........................................................................................................... .................... 55 10 copyri ght ...................................................................................................................... .............................. 91 11 disclai mer..................................................................................................................... .............................. 93 12 contact info rmation ............................................................................................................ ........................ 93 revision 1v3 4 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com revision history revision date owner description 0.99 6.10.2006 pkm corrected version 1.0 12.10.2006 pkm changed block diagram of dcdc15 inserted register o verview corrected some typos 1.1 26.1.2007 pkm corrected block diagram (dac mute) corrected start-up sequence (vprog1 and vprog2 exchange) 1.2 6.4.2007 pkm added typical application information changed chip version for v17 rtct register reset corrected to rvdd-por usb & chgin 0ms de-bounce time changed to 8ms 1.3 24.9.2008 pkm updated marking and ordering information revision 1v3 5 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 6 pinout and packaging 6.1 pin description table 1 pinlist ctbga81 ball pinname type function g7 agnd analog i/o analog reference voltage (avdd/2) buffer cap terminal h7 avdd supply analog circuit vdd, connected to ldo1 on bga substrate j9 avss supply analog circuit vss e2 battemp analog i/o charger battery temperature sensor input (100k ? ntc) d3 bvdd supply positive (battery) supply terminal, 5.5v max. e3 bvdd supply positive (battery) supply terminal, 5.5v max. b8 bvddh supply positive (battery) supply terminal of headphone amplifier, 5.5v max. a8 bvddc1 supply positive (battery) supply te rminal of dcdc1, 5.5v max. a4 bvddc2 supply positive (battery) supply te rminal of dcdc2, 5.5v max. b4 bvddc3 supply positive (battery) supply te rminal of dcdc3, 5.5v max. f2 bvddr supply rtc positive (battery) supply terminal, 5.5v max f1 chg_in analog input charger positive supply terminal, 5.5v max e1 chg_out analog output charger output prog. for ichg 50-400ma or vchg 3.9-4.25v c1 cn_gext digital output usb charge pump cn of flying cap / output to control usb-host dcdc n-switch c2 cp_cp digital output usb charge pump cp of flying cap g3 cscl digital input with pull up clock input of two wire interface h3 csda digital i/o with pull up data i/o of two wire interface b7 cvdd1 analog input cvdd1 and feedback pin b5 cvdd2 analog input cvdd2 and feedback pin b3 cvdd3 analog input cvdd3 and feedback pin a6 cvss1 supply cvdd1 stepdown neg. supply terminal b6 cvss2 supply cvdd2 stepdown neg. supply terminal a2 cvss3 supply cvdd3 stepdown neg. supply terminal b2 cvss15 supply dcdc15v neg. supply terminal g1 dvdd supply digital circuit vdd, connected to ldo2 on bga substrate j2 dvss supply digital circuit vss h2 fvdd supply adc&dac digital circuit vdd (1.8-3.6v) f3 hbt digital input with pull down heartbeat input for cpu supervision c8 hpcm analog output headphone common gnd output for dc-coupled speakers d9 hpgnd analog i/o headphone amplifier reference buffer cap terminal a9 hpl analog output headphone amplifier output left channel c9 hpr analog output headphone amplifier output right channel b1 isink analog output dcdc15v load current sink terminal (e.g. white led) d7 lin1l analog input line input 1 left channel d6 lin1r analog input line input 1 right channel f8 lin2l analog input line input 2 left channel f7 lin2r analog input line input 2 right channel c7 lout1l analog output line output left channel c6 lout1r analog output line output right channel d8 lout2l analog output line output left channel e7 lout2r analog output line output right channel g4 lrclk digital i/o with pull down i2s left/right clock a7 lxc1 digital output cvdd1 stepup switch output to coil a5 lxc2 digital output cvdd2 stepup switch output to coil a3 lxc3 digital output cvdd3 stepup switch output to coil revision 1v3 6 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com ball pinname type function h9 mic1n analog input microphone input 1n g9 mic1p analog input microphone input 1p g8 mic1s analog i/o microphone supply 1 (2.95v) / remote input 1 e9 mic2n analog input microphone input 2n f9 mic2p analog input microphone input 2p e8 mic2s analog i/o microphone supply 2 (2.95v) / remote input 2 d2 pvdd1 analog output ldo3 regulator output d1 pvdd2 analog output ldo4 regulator output f6 pwgd digital i/o multiplexed power good, spdif, pll clock, pwm digital output. configurable as open drain or push pull. master clk digital input (e.g. from cpu) j6 pwrup digital input with pull down power up input j4 q24m digital output multiplexed 12-24mhz clock output, pll clock. configurable as open drain or push pull. j3 q32k digital output multiplexed 32khz clock output, spdif, pll clock, pwm. configurable as open drain or push pull. g2 rvdd analog output rtc supply regulator output prog. to 1.0-2.5v f4 sclk digital i/o with pull down i2s shift clock h4 sdi digital input with pull down i2s data input to dac g5 sdo digital output i2s data output from adc a1 sw15 analog output dcdc15v switch terminal d4 usbh_csn analog input usb-host step up neg. current sense terminal to 100m ? resistor c4 usbh_csp analog input usb-host step up pos. current sense term. to 100m ? resistor (bvdd) c5 usbh_pg digital output output to control usb-host dcdc high side p-switch g6 vprg1 analog input 5 state prog input to define power up sequence h6 vprg2 analog input 5 state prog input to define default regulator voltages h8 vref analog i/o analog reference ( filtered avdd) decoupling cap terminal c3 vbus analog i/o usb supply terminal for supervision and charge pump or stepup feedback b9 vssh supply headphone amplifier neg. supply terminal j7 xin24 analog i/o 24mhz oscillator crystal terminal h1 xin32 analog i/o 32khz rtc oscillator crystal terminal h5 xirq digital output interrupt request output. configurable as open drain or push pull, active high or active low j8 xout24 analog i/o 24mhz oscillator crystal terminal j1 xout32 analog i/o 32khz rtc oscillator crystal terminal j5 xres digital output open drain reset output revision 1v3 7 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 6.2 ball assignment 6.2.1 ctbga81 figure 2 ball assignment ctbga81 1 2 3 4 5 6 7 8 9 a sw15 cvss3 lxc3 bvddc2 lxc2 cvss1 lxc1 bvddc1 hpl a b isink cvss15 cvdd3 bvddc3 cvdd2 cvss2 cvdd1 bvddh vssh b c cn_gext cp_cp vbus usbh_csp usbh_pg lout1r lout1l hpcm hpr c d pvdd2 pvdd1 bvdd usbh_csn nc lin1r lin1l lout2l hpgnd d e chg_out battemp bvdd nc nc nc lout2r mic2s mic2n e f chg_in bvddr hbt sclk nc pwgd lin2r lin2l mic2p f g dvdd rvdd cscl lrclk sdo vprg1 agnd mic1s mic1p g h xin32 fvdd csda sdi xirq vprg2 avdd vref mic1n h j xout32 dvss q32k q24m xr es pwrup xin24 xout24 avss j 1 2 3 4 5 6 7 8 9 revision 1v3 8 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 6.3 package drawings 6.3.1 ctbga81 marking figure 3 ctbga81 marking table 2 package code aywwzzz a y www zzz a ? for pb free year working week assembly/packaging free choice dimensions figure 4 ctbga81 9x9mm 0.8mm pitch revision 1v3 9 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 7 ordering information device id version temperature range package type delivery form AS3517H-ECTP v17 -20 to +85 c ctbga81; 9x9mm package size, 0 . 8mm ball pitch tape & reel drypack as3517h-ects v17 -20 to +85 c ctbga81; 9x9mm package size, 0 . 8mm ball pitch tray drypack revision 1v3 10 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 8 absolute maximum ratings (non-operating) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only. functional operation of the device at these or any other conditions beyond those indicated under ?operating conditions? i s not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. the device should b e operated under recommended operating conditions. table 3 absolute maximum ratings symbol parameter min max unit note v in_5v 5v pins -0.5 7.0 v applicable for pins bvdd, bvddh, bvddc1, bvdd c2, bvddc3, bvddr, chg_in, vbus v in_sw15 15v pin -0.5 17 v applicable for pin sw15 v in_vss voltage difference at vss terminals -0.5 0.5 v applicable for pins cvss3, cvss15, cvss1, cvss2, vssh, avss, dvss v in_dvdd 3.3v pins with diode to dvdd -0.5 5.0 dvdd+0.5 v applicable for pins lrck, sclk, sdi, vprg1, vprg2, battemp, isink, xin32, xout32, xin24, xout24, xirq, xres, pwgd, q32k, q24m, hbt v in_xdvdd pins with no diode to dvdd -0.5 7.0v v applicable for pins cscl, csda, pwrup v in_avdd 3.3v pins with diode to avdd -0.5 5.0 avdd+0.5 v applicable for pins hpcm, hpgnd, lout1l/r, lout2l/r, vref, agnd, lin1l/r, lin2l/r, mic1p/n, mic2p/n, mic1s, mic2s v in_reg voltage regulator pins with diodes to bvdd -0.5 5.0 bvdd+0.5 v applicable for pins avdd, dvdd, pvdd1/2, cvdd1/2/3, uvdd v in_rvdd voltage regulator pin with diode to bvdd -0.5 3.6 bvdd+0.5 v applicable for pins rvdd v in_bvdd pins with diode to bvdd -0.5 7.0 bvdd+0.5 v applicable for pins hpr/l, chg_out i scr input current (latchup immunity) -100 100 ma norm: jedec 17 esd electrostatic discharge hbm +/-1 kv norm: jedec jesd22-a114c p t total power dissipation (all supplies and outputs) 1000 mw bga81, t amb =70c h humidity non-condensing 5 85 % table 4 soldering conditions symbol parameter min max unit note t body package body temperature 260 c norm ipc/jedec j-std-020c, reflects mo i sture sensitivity level only t peak 235 245 c d well solder profile* 30 45 s above 217 c * austriamicrosystems ag strongly recommends to use underfill. revision 1v3 11 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 8.1 operating conditions 8.1.1 supply voltages table 5 operating conditions for supply voltages symbol parameter min max unit note bvddx battery supply voltage bvdd, bvddh, bvddc1, bvddc2, bvdd c3, bvddr 3.0 5.5 v vbus usb vbus voltage 4.0 5.5 v chg_in charger supply voltage 4.5 5.5 v dvdd digital supply voltage 2.8 3.6 v digital audio supply voltage (ldo2) avdd analogue supply voltage 2.8 3.6 v analog audio supply voltage (ldo1) agnd analogue ground voltage avdd/2 v delta - difference of negative supplie s cvss1, cvss2, cvss3, cvss 15, vssh, avss, dvss -0.1 0.1 v to achieve good performance, the n ega tive supply terminals should be connected to low impedance ground plane. v delta + difference of positive supplies -0.25 0.25 v avdd-dvdd table 6 electrical specification of other function blocks symbol parameter min typ max unit note v por_on power-on reset activation level 2.15 v power-on reset activation leve l when dvdd decreases v por_off power-on reset release level 2.0 v power-on reset release when dvdd increases v por_hy power-on hysterisis 100 mv f lrclk_wd lrclk frequency watchdog 2 4.1 8 khz t on_delay delay time of pin pwrup 10 ms minimum key press time v do_l digital output driver capability (drive low) 0.3 v pins xres, xirq, pwgd @ 8ma, sdo v do_h digital output driver capability (drive high) 2.6 v pins xres, xirq @ 8ma, pu sh/pull mode only, sdo i pu internal pull-up current source 10 a pins xres, xirq, pwgd v pwrup_l digital input level low, bvdd>3v 0.5 v pin pwrup v pwrup_h digital input level high, bvdd>3v bvvd/3 v pin pwrup v pwrup_h digital input level high, bvdd<=3v 1 v pin pwrup r pwrup internal pull-down resistor 360 k pin pwrup v di_l digital input level low dvdd/2 *0.3 0.42 v pin hbt, sdi, sclk, mclk , lrck v di_h digital input level high 1.02 dvdd/2 *0.7 v pin hbt, sdi, sclk, mclk , lrck i pd internal pull-down current source 10 a pin hbt f clk audio clock frequency 8 48 khz lrck according to st reamed audio data revision 1v3 12 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 8.1.2 operating currents table 7 supply currents symbol parameter typ max unit note i hph headphone current from bvddh 1 ma quiescent current, no load i dac->hp dac playback current 6.4 ma no load, including pmu i line->hp line input playback current 1.9 ma no load, including pmu 8.1.3 temperature range table 8 temperature range symbol parameter min typ max unit note t amb operating temperature range -20 25 85 c t j junction temperature range 0 110 c r th thermal resistance 39 c/w for ctbga81 package revision 1v3 13 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 8.1.4 audio specification table 9 audio parameters symbol parameter min typ max unit note dac input to line output fs full scale output 0.97 v rms 1khz fs input snr signal to noise ratio 91 db a-weighted, no load, silen ce input dr dynamic range 88 db a-weighted, no load, -6 0db fs 1khz input thd total harmonic distortion -90 db 1khz fs input sinad signal to noise and distortion 85 db a-weighted, 1khz fs input line input to line output fs full scale output 0.96 v rms 1khz 1v rms (fs) input snr signal to noise ratio 92 db a-weighted, no load, silen ce input thd total harmonic distortion -90 db 1khz 1v rms (fs) input sinad signal to noise and distortion 86 db a-weighted, 1khz fs input cs channel separation 89 db dac input to hp output 0.895 v rms r l = 32 fs full scale output 0.89 v rms r l = 16 snr signal to noise ratio 94 db a-weighted, no load, silen ce input dr dynamic range 90 db a-weighted, no load, -60d b fs 1khz input -95 db no load, 1khz fs input -75 db pout=20mw, r l = 32 , f=1khz fs input thd total harmonic distortion -69 -60 db pout=40mw, r l = 16 , f=1khz fs input 91 db a-weighted, no load, 1khz fs in put 73 db a-weighted,pout=20mw, r l = 32 , f=1khz fs input sinad signal to noise and distortion 68 db a-weighted,pout=40mw, r l = 16 , f=1khz fs input 74 db r l = 32 cs channel separation 68 db r l = 16 line input to hp output 0.875 v rms r l = 32 , 1khz 1v rms (fs) input fs full scale output 0.87 v rms r l = 16 , 1khz 1v rms (fs) input snr signal to noise ratio 95 db a-weighted, no load, silen ce input dr dynamic range 95 db a-weighted, no load, -60d b fs 1khz (fs) input -91 db no load, 1khz 1v rms input -75 db pout=20mw, r=32 , 1khz 1v rms (fs) input thd total harmonic distortion -70 -60 db pout=40mw, r=16 , 1khz 1v rms (fs) input sinad signal to noise and distortion 87 db a-weighted, no load, 1khz 1v rms input revision 1v3 14 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com symbol parameter min typ max unit note 74 db a-weighted, pout=20mw, r=32 , 1khz 1v rms (fs) input 68 db a-weighted, pout=40mw, r=16 , 1khz 1v rms (fs) input 75 db r l = 32 cs channel separation 70 db r l = 16 mic input to line output fs full scale output 0.97 v rms 1khz fs input snr signal to noise ratio 81 db a-weighted, no load, silen ce input dr dynamic range 83 db a-weighted, no load, -60d b fs 1khz input thd total harmonic distortion -78 db 1khz 27mv rms (-3db fs) input sinad signal to noise and distortion 75 db a-weighted, 1khz 27mv rms (-3db fs) input line input to adc output snr signal to noise ratio 90 db a-weighted, no load, silen ce input dr dynamic range 90 db a-weighted, no load, -60d b fs 1khz input thd total harmonic distortion -78 db 1khz 1v rms (-3db fs) input sinad signal to noise and distortion 78 db a-weighted, 1khz 1v rms (- 3db fs) input revision 1v3 15 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9 detailed functional description 9.1 audio functions 9.1.1 audio line inputs (2x) general the chip features includes two identical lin e inputs. the blocks can work in mono differential, 2x mono single ended or in ster eo single ended mode. the volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5db each and mute. the gain can be set from ?34.5db to +12db. the stage is set to mute by defaul t. if the line input is not enabled, the volume settings are set t o their default values. changing the volume and mute control can only be done after enabling the input. figure 5 line inputs stereo mode mono single ended mode mono differential mode revision 1v3 16 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com parameter table 10 line input parameter symbol parameter min typ max unit note v lin input signal level 1.0 v peak pls observe gain settings. max. peak levels at any node within the circuit shall not exceed avdd r lin input impedance 20-100 k ? depending on gain setting rlin input impedance tolerance 15 % c lin input capacitance 5 pf a lin programmable gain -34.5 +12 db gain steps 1.5 db discrete logarithmic gain steps gain step accuracy 0.25 db a linmute mute attenuation 100 db bvdd = 3.3v, t a = 25 o c, fs=48khz unless otherwise mentioned register description table 11 line input related register name base offset description line_in1_r 2-wire serial 0ah right line input 1 settings line_in1_l 2-wire serial 0bh left line input 1 settings line_in2_r 2-wire serial 0ch right line input 2 settings line_in2_l 2-wire serial 0dh left line input 2 settings audioset_1 2-wire serial 14h enable/disable driver stage audioset_3 2-wire serial 16h enable/disable mixer input line inputs have to be enabled in register 14h first before other settings in register 0ah to 0dh can be programmed. revision 1v3 17 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.1.2 microphone inputs (2x) general the afe offers two microphone inputs and 2 low noise microphone voltage supply (microphone bias), voice activation, microphone connect detection and push button remote control. figure 6 microphone input microphone preamplifier and gain stage gain stage & limiter the integrated pre-amplifier allows 3 preset gain settings. there is also a limiter which attenuates high input signals from e. g. electrete microphones signal to 1vp. the agc has 15 steps with a dynamic range of about 29db. the agc is on by default but can be disable d by a microphone register bit. apart from the microphone pre-amplifier the microphone input signal can further be amplified with 32 @1.5db programmable logari th mic gai n steps and mute. all gains and mute are independently programmable. the gain can be set from ?40.5db to +6db. the stage is set to mute by default. if the microphone input is not enabled, the volume settings are set to their default value s. ch anging the volume and mute control can only be done after enabling the input. supply & detection each microphone input generates a supply voltage of 1.5v above hphcm. the supply is designed for 2ma and has a 10ma current limit. in off mode the mics terminal is pulled to avdd with 30kohm. a current of typically 50ua generates an interrupt to infor m the cpu, that a circuit is connected. when using hpcm as headset ground the hp?stage gives the interrupt. after enabling the hp-sta ge through the cpu the microphone detection interrupt will follow. when using the micxs terminals as adc-10 input to monitor external voltages the 30kohm pull-up can be disabled. remote control fast changes of the supply current of typically 500ua are detected as a remote button press, and an interrupt is generated. the n the cpu can start the measurement of the microphone supply current with the internal 10-bit adc to distinguish which button was pressed . as the current measurement is done via an internal resistor, only two buttons generating a current of about 0.5ma and 1ma can be detec ted. with this 1ma as microphone bias is still available. voice activation further a built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mvrms is detected . revision 1v3 18 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com parameter table 12 microphone inputs parameter symbol parameter min typ max unit note v micin 0 40 mv peak a micpre = 28db; a mic = 0db v micin 1 20 mv peak a micpre = 34db; a mic = 0db v micin 2 input signal level 10 mv peak a micpre = 40db; a mic = 0db r micin input impedance 15 k? micp, micn to agnd micin input impedance tolerance 15 % c micin input capacitance 5 pf a micpre microphone preamplifier gain 28 34 40 db db db preamplifier has 3 sele ctable (fixed) gain settings a mic programmable gain -40.5 +6 db gain steps 1. 5 db discrete logarithmic gain steps gain step precision 0.25 db v miclimit limiter activation level 1 v peak a miclimit limiter gain overdrive 15*2 db t attack limiter attack time 50 s/6db t decay limiter decay time 120 ms/6db a micmute mute attenuation 100 db v micsup microphone supply voltage 2.9 v i micmax max. microphone supply current 10 ma microphones nominally nee d a bias current of 0.5ma-1ma v noise microphone supply voltage noise 5 v i micdet microphone detection current 50 a i remdet max. remote detection current 500 a bvdd = 3.3v, t a = 25 o c unless otherwise mentioned register description table 13 microphone related register name base offset description mic1_r 2-wire serial 06h right microphone input 1 volume settings, agc control mic1_l 2-wire serial 07h left microphone input 1 volume settings, mic 1 supply control mic2_r 2-wire serial 08h right microphone input 2 volume settings, agc control mic2_l 2-wire serial 09h left microphone input 2 volume settings, mic 2 supply control audioset_1 2-wire serial 14h enable/disable driver stage audioset_3 2-wire serial 16h enable/disable mixer input irq_enrd_1 2-wire serial 24h interrupt settings for microphone voice activation irq_enrd_3 2-wire serial 26h interrupt settings for microphone detection irq_enrd_4 2-wire serial 27h interrupt settings for remote button press detection microphone inputs have to be enabled in register 14h first before other settings in register 06h to 09h can be programmed. revision 1v3 19 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.1.3 audio line outputs (2x) general the line outputs are designed to provide the audio signal with typical 1v peak at a load of minimum 10k , which is a minimum value for line inputs. if the limiters (n20/n21) are deactivated the peak output voltage is 1.45v peak . the load however can decrease to 64ohm. in addition these line output can be configured as mono differential to drive 1v peak @ 32 load (e.g. an earpiece of a mobile phone). this output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be set from -40.5d b to +6db. a zero cross detection allows to control the actual execution of new gain settings. if the line output is not enabled, the volume settings are set to their default values. changing of volume and mute control can only be done after enabling the output. if using the output in mono differential mode, the volume setting for the right channel should be set to 0db. figure 7 line output stereo mode mono differential mode (please observe that gain of right ch anne l amplifier has to best to 0db) parameter table 14 line output characteristics symbol parameter min typ max unit note r l_lo load impedance (stereo mode) 64 line inputs nominally have 10k c l_lo load capacitance (stereo mode) 100 pf a lo programmable gain -40.5 +6 db gain steps 1. 5 db discrete logarithmic gain steps gain step accuracy 0.25 db a lomute mute attenuation 100 db bvdd = 3.3v, t a = 25 o c unless otherwise mentioned register description table 15 line output related register name base offset description line_out1_r 2-wire serial 00h right line output 1 volume settings, mux control line_out1_l 2-wire serial 01h left line output 1 volume settings line_out2_r 2-wire serial 04h right line output 2 volume settings, mux control line_out2_l 2-wire serial 05h left line output 2 volume settings audioset_1 2-wire serial 14h enable/disable driver stage audioset_3 2-wire serial 16h enable/disable mixer input line output have to be enabled in register 14h first before other settings in register 00h and 01h can be programmed. revision 1v3 20 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.1.4 headphone output general the headphone output is designed to provide the audio signal with 2x40mw @ 16 or 2x20mw @32 , which are typical values for headphones. if the limiters (n20/n21) are disabled a maximum output of 2x60mw@16 or 2x30mw@32 can be achieved. this output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be set from ? 43.4 3db to +1.07db. a zero cross detection allows to control the actual execution of new gain settings. figure 8 headphone output headphones connected via decoupling capacitors headphones connected to phantom ground (common mode) phantom ground there are 2 ways to connect a headphone to the afe. in order to spare the bulky ac/dc decoupling capacitors at pins hpr/hpl a buffered ground (phantom ground) is provided. this common mode buffer needs to be switched on if utilized. if form factor considerations are less stringent, the headphones can be conventionally connected via 2x100f capacitors. no-pop function the output is automatically set to mute when the output stage is disabled. to avoid pop-click noise during power-up and shut-down of the h ead phone amplifier, a charge/discharge control of hpgnd (0v-1.45 v- 0v) at pins hpr/hpl is incorporated into the afe. the 100nf capacitor at pin hpgnd is used to form the charge/discharge slope. pls observe that pin hpgnd is a high impedance node which must not be connected to any other external device than the 100nf buffer capacitor. to avoid pop-click noise one has to wait for 150ms in between a power-down (switch-off) and a power-up (switch-on) o f the headphone amplifier. the output is automatically set to mute when the output stage is disabled. figure 9 hp pop-click suppression t hpgnd [v] 70ms 70ms agnd mute off hp amps powered down o p eration revision 1v3 21 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com over-current protection the headphone amplifier has an over-current protection (e.g. hpr/hp l is shorted). this over-current protection will power the h eadphone amplifier down for a programmable timeout period (512ms, 256ms, 128ms). the current threshold is at 150ma for hpr/hpl and 300ma for hpcm. there is a corresponding interrupt available to be enabled. headphone detection when the headphone amplifier is powered down, one can detect the connection of a headset. it only work if the headset is connec ted between pins hpr/hpl and hpcm. as long as the headphone amplifier is powered down, hpcm is biased to 150mv and acting as the sense pin. there is a corresponding interrupt available to be enabled. power save options to save power, especially when driving 32 ohm loads, a reduction of the bias current can be selected. together with switching off the phantom ground this gives 4 possible operating modes. table 16 headphone power-save options hpcm_off ibr_hph idd_hph (typ.) load 0 0 2.2ma 16 o hm 1 0 1.5ma 16 o hm 0 1 1.5ma 32 o hm 1 1 1.0ma 32 o hm bvdd = 3.3v, t a = 25 o c unless otherwise mentioned parameter table 17 power amplifier block characteristics symbol parameter min typ max unit note r l_hp load impedance 16 ? stereo mode c l_lo load capacitance 100 pf stereo mode p hp nominal output power 40mw 20 mw rl=16 ? , limiter enabled rl=32 ? , limiter enabled p hp_max max. output power 60mw 30 mw rl=16 ? rl= 32 ? a lo programmable gain -45.5 +1 db gain s teps 1.5 db discrete logarithmic gain step s gain step accuracy 0.25 db over c urrent limit 150 30 0 ma ma hpr/hpl pins hpcm pin p srrhp power supply rejection ratio 90 db 200hz-20khz, 720mvpp, rl= 16 ? a lomute mute attenuation 100 db bvdd = 3.3v, t a = 25 o c unless otherwise mentioned register description table 18 headphone related register name base offset description hph_out_r 2-wire serial 02h right hp output volume and over-current settings hph_out_l 2-wire serial 03h left hp output volume settings, enable and detection control audioset_3 2-wire serial 16h power save options, common mode buffer irq_enrd_3 2-wire serial 26h interrupt settings for over current and hp detection revision 1v3 22 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.1.5 dac, adc and i2s digital audio interface input the afe receives serialized audio data for the dac via pin sdi. the output of the dac is fed through a volume control to the mi xer stage and to the multiplexers of line output and headphone amplifiers. this serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-s tream . via pin lrclk the alignment clock is input to the dac digital filters. lrclk (left right clock) indicates whether the serial bit-stream received via pin sdi, represents right channel or left channel audio data. via pin sclk the bit clock for the serial bit-stream is signalled . sdi and lrclk are synchronous with sclk. sdi is an inputs; lrclk and sclk are either inputs or outputs depending on the master/slave operation mode. sdo is not used. the volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be se t fro m ? 40.5db to +6db. the stage is set to mute by default. if the dac input is not enabled, the volume settings are set to their defa ult values. changing the volume and mute control can only be done after enabling the input. output this block consists of an audio multiplexer where the signal, which should be recorded, can be selected. the output is then fed through a volume control to the 20 bit adc. the digital output is done via an i2s interface. the afe sends serialized audio data from the adc via pin sdo. this serialized audio data is a digital audio data stream with th e le ft and the right audio channels multiplexed into one bit-stream. via pin lrclk the alignment clock is signalled to the connected devic es (e.g. cpu). lrclk (left right clock) indicates whether the serial bit-stream sent via pin sdi, presents right channel or left channel audio data. via pin sclk the bit clock for the serial bit-stream is signalled. sdo and lrclk are synchronous with sclk. sdo is an output; l rclk and sclk are either inputs or outputs depending on the master/slave operation mode. sdi is not used. the volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be se t fro m ? 34.5db to +12db. the stage is set to mute by default. if the adc output is not enabled, the volume settings are set to their de fault values. changing the volume and mute control can only be done after enabling the input. the i2s output uses the same clocks as the i2s input. the sampling rate therefore depends also on the input sampling rate. i2s modes the afe can be operated either in master mode, slave mode or additionally in slave mode with the master clock directly signalle d via pin pwgd (pin pwgd is multiplexed for i2s direct mode). the difference between master and slave mode is whether the afe or the externally attached decoder/encoder device is generating the interface clocks. the master clock (mclk) is the necessary interna l over- sampling clock for the dac and adc (e.g. 256*fs, fs=audio sampling frequency). due to the internal structure left and right audio samples are exchanged in i2s direct mode. in slave mode the pll generates the master clock based on lrclk. thus the pll needs to be preset to the expected sampling frequ ency. the ranges are 8ks-12ks (8khz-12khz) and 16ks-48ks (16khz-48khz). please refer to register 0x1dh. table 19 i2s modes master mode slave mode, internal pll of the afe generates mclk slave mode with i2s direct, the master clock is signalled revision 1v3 23 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com via pin pwgd power save options the bias current of the dac block can be reduced in three steps down to 50% to reduce the power consumption. clock supervision the digital audio interface automatically checks the lrclk. an interrupt can be generated when the state of the lrclk input cha nges. a bit in the interrupt register represents the actual state (present or not present) of the lrclk. signal description the digital audio interface uses the standard i2s format: ? le ft justified ? ms b first ? o ne additional leading bit the first 18 bits are taken for dac conversion. the on-chip synchronization circuit allows any bit-count up 32bit. when there a re less than 18 bits sampled, the data sample is completed with ?0?s. in i2s direct mode the data length has to be minimum 18 bits. the adc output is always 20 bit. if more sclk pulses are provided, only the first 20 will be significant. all following bits wi l l be ?0?. sclk has not to be necessarily synchronous to lrclk but the high going edge has to be separate from lrclk edges. the lrck signa l has to be derived from a jitter-free clock source, because the on-chip pll is generating a clock for the digital filter, which has to be always in correct phase lock condition to the external lrclk. please observe that in slave mode lrclk has to be activated before enabling the adc. in master mode operation sclk has 32 clock cycles for each sample word. 64* 4 256* 4 lrck lrclk mclk sclk = == sample rates in master mode as3517 allows programming various sample rates. the master clock is generated by the 12-24mhz oscillator. sampli ng frequencies from 8khz to 48khz can be selected. for certain division ratios between master clock and sample ratio a certain dev iation is system inherent. 2 1 * 2*)1 ( 1 * + + = rd pllmode flrclk osc )5110( ................. )2,1( ...... ................ ? rratedivide rd factorpll pllmode frequency lator quarzoscil f osc revision 1v3 24 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 20table 21 i2s master clock pll settings f osc fsample (lrck) pll-mode rd (rate divider) deviation 24mhz 48.00ks 1 123 0.00% 24mhz 44.10ks 1 134 0.04% 24mhz 32.00ks 1 186 -0.27% 24mhz 24.00ks 1 248 0.00% 24mhz 22.05ks 1 270 0.04% 24mhz 16.00ks 1 373 0.00% 24mhz 12.00ks 2 248 0.00% 24mhz 11.025ks 2 270 0.04% 24mhz 8.00ks 2 373 0.00% f osc fsample (lrck) pll-mode rd (rate divider) deviation 16mhz 48.00ks 1 81 0.40% 16mhz 44.10ks 1 179 -0.33% 16mhz 32.00ks 1 123 0.00% 16mhz 24.00ks 1 165 -0.20% 16mhz 22.05ks 1 179 0.22% 16mhz 16.00ks 1 248 0.00% 16mhz 12.00ks 2 165 -0.20% 16mhz 11.025ks 2 179 0.22% 16mhz 8.00ks 2 248 0.00% f osc fsample (lrck) pll-mode rd (rate divider) deviation 12mhz 48.00ks 1 61 -0.79% 12mhz 44.10ks 1 66 0.04% 12mhz 32.00ks 1 92 0.27% 12mhz 24.00ks 1 123 0.00% 12mhz 22.05ks 1 134 0.04% 12mhz 16.00ks 1 185 0.27% 12mhz 12.00ks 2 123 0.00% 12mhz 11.025ks 2 134 0.04% 12mhz 8.00ks 2 185 0.27% parameter figure 10 i2s left justified mode revision 1v3 25 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 11 i2s timing table 22 audio converter parameter symbol parameter min typ max unit note t sclk sclk cycle time 160 ns t sclkh sclk pulse width high 80 ns t sclkl sclk pulse width low 80 ns t lrsu lrclk setup time before sclk rising edge 80 ns t lrhd lrclk hold time after sclk rising edge 80 ns t sdsu sdi setup time before sclk rising edge 25 ns t sdhd sdi hold time after sclk rising edge 25 ns t sdod sdo delay from sclk falling edge 25 ns t jitter jitter of lrclk -20 20 ns internal pll generates mc lk from lrclk i2s direct mode t scd sclk delay after mclk rising edge 0.5 1.5 ns t lrd lrlck delay after sclk rising edge 0.5 1.5 ns t sdsu sdi setup time before sclk rising edge 5 ns t sdhd sdi hold time after sclk rising edge 5 ns t sdod sdo delay from sclk falling edge 15 ns v i2sh sclk, lrclk, sdi, mclk high input level 1.02 v dvdd/2*0.7 v i2sl sclk, lrclk, sdi, mclk low input level 0.42 v dvdd/2*0.3 v sdoh sdo high output level 2.6 v at 2ma v sdol sdo low output level 0.3 v at 2ma v i2soh sclk, lrclk, high output level 2.6 v at 8ma master mode only v i2sol sclk, lrclk, low output level 0.3 v at 8ma master mode only bvdd=3.3v, t a =25c, slave mode, f s =48khz, mclk = 256*f s, unless otherwise specified revision 1v3 26 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com register description table 23 audio converter related register name base offset description dac_r 2-wire s erial 0eh dac input volume settings dac_l 2-wire serial 0fh dac input volume settings adc_r 2-wire serial 10h adc output volume settings, source multiplexer settings adc_l 2-wire serial 11h adc output volume settings i2s 2-wire serial 1eh i2s master mode settings i2s_pll_osc 2-wire serial 1dh i2s master mode and pll settings audioset_1 2-wire serial 14h enable/disable adc audioset_2 2-wire serial 15h enable/disable dac and power save options audioset_3 2-wire serial 16h enable/disable mixer input irq_enrd_1 2-wire serial 25h interrupt settings for lrck changes dac and adc have to be enabled in register 14h first before other settings in register 0eh to 11h can be programmed. revision 1v3 27 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.1.6 audio output mixer general the mixer stage sums up the audio signals of the following stages ? m icrophone input 1 & 2 (stereo microphone) ? l ine input 1 ? l ine input 2 ? di gital audio input (dac) the mixing ratios have to be with the volume registers of the corresponding input stages. please be sure that the input signals of the mix er stage are not higher than 1vp. if summing up several signals, each individual signal has of course to be accordingly lowe r. this shall insure that the output signal is also not higher than 1vp to get a proper signal for the output amplifier. this stage features an automatic gain control (agc), which automatically avoids clipping. register description audio mixer related register name base offset description audioset_2 2-wire serial 15h enable/disable mixer stage and agc audioset_3 2-wire serial 16h enable/disable dac, mic or line inputs to mixer stage revision 1v3 28 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.1.7 2-wire-serial control interface general there is an i2c slave block implemented to have access to 64 byte of setting information. the i2c address is: adr_group8 - audio processors ? 8c h_write ? 8d h_read protocol table 24 i2c symbol definitions symbol definition r/w (as3517 slave) note s start condition after stop r 1 bit sr repeated sta rt r 1 bi t dw device address for write r 1000 1100b (8ch) dr device address for read r 1000 1101b 8dh) wa word add ress r 8 bi t a acknowledge w 1 b it n no acknowledge r 1 bit reg_data register data/write r 8 bit data (n) register data/read w 8 bit p stop c ondition r 1 b it wa++ increment word address internally r during acknowledge as3517 (=slave) receives data as3517 (=slave) transmits data figure 12 byte write figure 13 page write byte write and page write formats are used to write data to the slave. the transmission begins with the start condition, which is generated by the master when the bus is in idle state (the bus is fr ee). t he device-write address is followed by the word address. after the word address any number of data bytes can be sent to the slave. the word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. for reading data from the slave device, the master has to change the transfer direction. this can be done either with a repeate d s tart condition followed by the device-read address, or simply with a new transmission start followed by the device-read address, whe n the bus is in idle state. the device-read address is always followed by the 1st register byte transmitted from the slave. in read m ode any number of subsequent register bytes can be read from the slave. the word address is incremented internally. revision 1v3 29 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 14 random read random read and sequential read are combined formats. the repeated start condition is used to change the direction after the da ta transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is idle. the start condition i s followed by the device-write address and the word address. in order to change the data direction a repeated start condition is issued on the 1st scl pulse after the acknowledge bit of th e word addr ess transfer. after the reception of the device-read address, the slave becomes the transmitter. in this state the slave tr ansmits register data located by the previous received word address vector. the master responds to the data byte with a not-acknowledge , and issues a stop condition on the bus. figure 15 sequential read sequential read is the extended form of random read, as more than one register-data bytes are transferred subsequently. in diff erenc e to the random read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. the number of data bytes transferred in one sequence is unlimited (consider the behaviour of the word-address counter). to terminat e the transmission the master has to send a not-acknowledge following the last data byte and generate the stop condition subsequently . figure 16 current address read to keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the dat a transfer. the bus is idle and the master issues a start condition followed by the device-read address. analogous to random read , a single byte transfer is terminated with a not-acknowledge after the 1st register byte. analogous to sequential read an unlimite d number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. for termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent stop condition. revision 1v3 30 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com parameter figure 17 i2c timing table 25 i2c operating conditions symbol parameter min typ max unit notes v csl cscl, csda low input level 0 - 0.87 v (max 30%dvdd) v csh cscl, csda high input level 2. 03 - 5.5 v cscl, csda (min 70 %dvdd) hyst cscl, csda input hysteresis 200 450 800 mv v ol csda low output level - - 0.4 v at 3ma tsp spike insensitivity 50 100 - ns t h clock high time 500 ns max. 400khz clock speed t l clock low time 500 ns max. 400khz clock speed t su 250 - - ns csda has to change tsetup b efore rising edge of cscl t hd 0 - - ns no hold time needed for csda rela tive to rising edge of cscl ts 200 - - ns csda h hold time relative to csda edg e for start/stop/rep_start t pd 50 ns csda prop delay relative to l owgoing edge of cscl dvdd =2.9v, t amb =25oc; unless otherwise specified revision 1v3 31 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.2 power management functions 9.2.1 low drop out regulators general these ldo?s are designed to supply sensitive analogue circuits, audio devices, ad and da converters, micro-controller and other peripheral devices.the design is optimised to deliver the best compromise between quiescent current and regulator performance f or battery powered devices. stability is guaranteed with ceramic output capacitors of 1 f +/ -20% (x5r) or 2.2 f +100/-50% (z5u). the low esr of these caps ensures low output impedance at high frequencies. regulation performance is excellent even under low dropout conditions, when t he power transistor has to operate in linear mode. power supply rejection is high enough to suppress high ripple on the battery at the output. the low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. the low i mpedance of the power device enables the device to deliver up to 150ma even at nearly discharged batteries without any decrease of performa nce. figure 18 ldo block diagram ldo1 this ldo generates the analog supply voltage used for the afe itself. x i nput voltage is bvdd x ou tput voltage is avdd (typ. 2.9v) x dri ver strength: 200ma it is set to a fixed output voltage of 2.9v, 200ma max . it supplies the analog part of the afe. additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. furt her the external load must not induce n oise to the sensitive avdd supply pin. ldo2 this ldo generates the digital supply voltage used for the afe itself. x i nput voltage is bvdd x out put voltage is dvdd (typ. 2.9v) x dri ver strength: 200ma it is set to a fixed output voltage of 2.9v, 200ma max . it supplies the digital part of the afe. additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. furt her the external load must not induce n oise to the dvdd supply pin but is not as critical as avdd. ldo3 & ldo4 these ldo can used to generate the periphery voltage for the digital processor or other external components (e.g. ext. dac, usb -phy, sd-cards, nand-flashes, fm-tuner ?) x i nput voltage bvdd x ou tput voltage is pvdd1 & pvdd2 (1.2 to 3.5v) x de fault value at start-up is defined by vprog1 and vprog2 pins x dri ver strength: 200ma revision 1v3 32 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com parameter table 26 ldos block characteristics symbol parameter min typ max unit notes r on on resistance 1 ? 70 db f=1khz psrr power supply rejection ratio 40 db f=100khz i off shut down current 100 na i vdd supply current 50 a without load noise output noise 50 v rms 10hz < f < 100khz t start startup time 200 s v out_tol output voltage tolerance -50 50 mv <1 mv ldo1, static v linereg line regulation <10 mv ldo1, transient;slope: t r =10 s <1 mv ldo1, static v loadreg load regulation <10 mv ldo1, transient;slope: t r =10 s i limit current limitation 400 ma ldo1, ldo2, ldo3, ldo4 bvdd=4v; i load =150ma; t amb =25oc; c load =2.2 f (ceramic); unless otherwise specified figure 19 typical performance characteristics load regulation output noise transient load: 1ma ? 100ma slope: 1 s output load: 150ma revision 1v3 33 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com load regulation load regulation output load: 10ma transient input voltage ripple: 500mv output load: 150ma transient input voltage ripple: 500mv register description table 27 ldo related register name base offset description pmu pvdd1 2-wire serial 17h-1 pvdd1 (ldo3) control and voltage settings pmu pvdd2 2-wire serial 17h-2 pvdd2 (ldo4) control and voltage settings pmu enable 2-wire serial 18h enables writings to extended registers 17h-1, 17h-2 revision 1v3 34 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.2.2 dcdc step-down converter (3x) general these converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors. ? inpu t voltage bvddc1, bvddc2 & bvddc3 (u sually connected to the battery) ? output voltage cvdd1, cvdd2 & cvdd3 ? o utput voltage levels can be programmed independently form 0.65v to 3.4v ? t he default value at start-up is defined by vprog1 and vprog2 pins ? dr iver strength 250ma (500ma for dcdc 3) figure 20 dcdc step-down block diagram functional description the step-down converter is a high efficiency fixed frequency current mode regulator. by using low resistance internal pmos and nmos switches efficiency up to 97% can be achieved. the fast switching frequency allows using small inductors, without increasing th e current ripple. the unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage ra nge, up to an output current of 250ma, with an output capacitor of only 10 f. the implemented curre nt limitation pr otects the dcdc and the coil during overload condition. to achieve optimised performance in different applications, adjustable settings allow to compromise between high efficiency and low inp ut, output ripple: low ripple, low noise operation: in this mode there is no minimum coil current necessary before switching off the pmos. as result, the on time of the pmos will be reduc ed down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. this results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. esp ecially in the case of an inverted coil current the regulator will not operate in pulse skip mode. revision 1v3 35 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 21 ?dcdc buck with disabled current force / pulse skip mode 1: lxc1 voltage, 2:coil current (1mv=1ma) 3: output voltage high efficiency operation: in this mode there is a minimum coil current necessary before switching off the pmos. as result, fewer pulses at low output loads are nec essary, and therefore the efficiency at low output load is increased. on the other hand the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current. figure 22 ?dcdc buck with enabled current force / pulse skip mode 1: lxc1 voltage, 2:coil current (1mv=1ma) 3: output voltage it?s also possible to switch between these two modes dynamically during operation: 100% pmos on mode for low dropout regulation: for low input to output voltage difference the dcdc converter ca n u se 100% duty cycle for the pmos transistor, which is then in ldo mode. this feature is enabled if the output voltage drops by more than 4%. revision 1v3 36 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com parameter table 28 dcdc buck typical performance parameter symbol parameter min typ max unit notes v in input voltage 3.0 5.5 v bvdd v out regulated output voltage 0.65 3.4 v v out_tol output voltage tolerance -50 50 mv 250 ma dcdc 1&2 i load maximum load current 500 ma dcdc 3 450 ma dcdc 1&2 i limit current limit 800 ma dcdc 3 0.5 0.7 bvdd=3.0v; dcdc 1&2 r psw p-switch on resistance 0.34 0.7 bvdd=3.0v; dcdc 3 0.5 0.7 bvdd=3.0v; dcdc 1&2 r nsw n-switch on resistance 0.37 0.7 bvdd=3.0v; dcdc 3 f sw switching frequency 1.2 mhz f swsc switching frequency 0.6 mhz in shortcut case c out output capacitor 10 f ceramic, +/- 10% tolerance lx inductor 3.3 4.7 h +/- 10% tolerance eff efficiency 97 % iout=100ma, vou t=3.0v i vdd current consumption 220 10 0 0.1 a operating current without load low power mode current shutdown current t min_on minimum on time 80 ns t min_off minimum off time 40 ns 2 mv static v linereg line regulation 10 mv transient; slope: t r =10 s, 100mv step, 200ma load 5 mv static v loadreg load regulation 50 mv transient; slope: t r =10 s, 100ma step bvdd=3.6v; t amb =25oc; unless otherwise specified figure 23 dcdc step-down performance characteristics revision 1v3 37 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com register description table 29 dcdc buck related register name base offset description pmu cvdd1 2-wire serial 17h-3 cvdd1 (dcdc1) control and voltage settings pmu cvdd2 2-wire serial 17h-4 cvdd2 (dcdc2) control and voltage settings pmu cvdd3 2-wire serial 17h-5 cvdd2 (dcdc2) control and voltage settings pmu enable 2-wire serial 18h enables writings to extended registers 17h-3, 17h-4 revision 1v3 38 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.2.3 charger general this block can be used to charge a 4v li-io accumulator. it supports constant current and constant voltage charging modes with adjustable charging currents (50 to 400ma) and maximum charging voltage (3.9 to 4.25v). figure 24 charger states trickle charge if bvdd is below 3v in systems where the batte ry is not separated from bvdd, the charge r goes automatically in trickle charge m ode with 50ma charging current and 3.9v endpoint voltage. in this mode charging current and voltage are not precise, but provide a charg er function also for deep discharged batteries. the temperature supervision is not enabled in trickle charge mode. as soon as bvdd reaches 3v the afe switches on and starts-up the regulators with the power-up sequence selected by pins vprg1 a nd vprg2. afterwards the cpu can set the modes and the charging currents via the 2-wire serial interface. if the battery (chgout) voltage is below 2.9v the charging curre nt c annot be set higher than 50ma, also when using a battery se paration circuit to supply the afe (bvdd) from usb or another voltage source. temperature supervision this charger block also features a 15ua supply for an external 100k ntc resistor to measure the battery temperature while charging. if the temperature is too high (>45c), an interrupt can be generated. if the battery temperature drops below 42c the charger wil l start charging again. the temperature supervision is not enabled in trickle charge mode. if the ntc resistor does not have 100k ? its value can be corrected with a resistor in series or in parallel. revision 1v3 39 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com parameter table 30 charger parameter symbol parameter min typ max unit notes 37 68 111 ma bvdd<=3v, chgin = 5.5v i chg_trick charging current (trickle charge) 17 32 55 ma bvdd<=3v, chgin = 4.0v v chg_trick charger endpoint voltage (trickle charge) 0.70* chgin 0.72* chgin 0.74* chgin v bvdd<=3v, chgin = 4.4v i chg (0-7) charging current i nom -20% i nom i nom +20% ma bvdd > 3v v chg (0-7) charging voltage v nom -50mv v nom v nom +30mv v bvdd > 3v, end of charge is true v on_abs charger on voltage irq 3.1 4.0 v bvdd = 3v v on_rel charger on voltage irq 170 240 mv chgin-chgout v off_rel charger off voltage irq 40 77 mv chgin-chgout v batemp_on battery temp. high level (45c) 610 mv bvdd >3v v batemp_off battery temp. low level (4 2c) 700 mv bvdd >3v i chg_off end of charge current level 5% i nom 10% i nom 15% i nom ma bvdd >3v i rev_off reverse current shut down <1 ua bvdd = 5v, chgin open bvdd=3.6v; t amb =25oc; unless otherwise specified register description table 31 charger related register name base offset description charger 2-wire serial 22h charger voltage, current and temp. supervision control irq_enrd_2 2-wire serial 25h enable/disable eoc and battery over-temperature interrupt read out charger status revision 1v3 40 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.2.4 15v step-up converter general the integrated step-up dc/dc converter is a high efficiency current-mode pwm regulator, providing an output voltage up to 15v. a constant switching-frequency results in a low noise on supply and output voltages. when using an additional transistor the outp ut voltage can be up to 25v to drive 6 white led in series. it has an adjustable sink current (1.25 to 37.5ma) to provide e.g. dimming function when driving white leds as back-light. figure 25 dcdc15 block diagram parameter table 32 15v step-up converter parameter symbol parameter min typ max unit notes v sw high voltage pin 0 15 v pin sw15 i vdd quiescent current 140 a pulse skipping mode v fb feedback voltage, transient 0 5.5 v pin isink v fb feedback voltage, during regulation 0.65 0.83 1.0 v pin isink i sw_max current limit 350 510 750 ma v15_on = 1 r sw switch resistance 0.85 1.54 v15_on = 0 i load load current 0 45 ma @ 15v output voltage v pulseskip pulse-skip threshold 1.2 1.33 1.5 v voltage at pin isink, pulse skips are i ntroduces when load current becomes too low. f in fixed switching frequency 0.5 0.55 0.6 mhz c out output capacitor 1 f ceramic i load > 20ma 17 22 27 h use inductors with small c parasitic (<100pf) for high efficency l (inductor) i load < 20ma 8 10 27 t min_on minimum on-time 90 180 ns guaranteed per design mdc maximum duty cycle 85 91 98 % guaranteed per design bvdd=3.6v; t amb =25oc; unless otherwise specified revision 1v3 41 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 26 15v step-up performance characteristics efficiency vs output current 50 55 60 65 70 75 80 85 90 95 100 1 10 100 output current [ma] efficiency [%] dcdc stepup current controlled 0..15v v in =3,6v load: 3 led's register description table 33 15v step-up related register name base offset description dcdc15 2-wire serial 1bh dcdc15 c urrent and dimming control revision 1v3 42 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.2.5 usb vbus supply the vbus voltage converter consists out of a charge pump and a dcdc converter. these 2 blocks share common pins. the charge pump (cp) and is used as usb-otg (on the go) supply (5v/8ma) and the dcdc st ep-up converter provides the usb-host supply (5v /500ma). depending on the external config uration either cp mode or dcdc mode is sele cted. be aware that only one block can be u sed in one application. the following description shows how each block operates and how the circuit should be configured. additional the usb vbus generation block features a vbus comparator to d etect different vbus levels thus complies to srp (sessi on request protocol) and hnp (host negotiation protocol). vbus dcdc (usb host supply) with the pin usbh_csp connected to the bat tery voltage the mode usb-host mode is selected. this me ans the dcdc converter supplies 5v and up to 500ma. for device safety an external pmos switch is necessary in the case of a short-circuit condition on the vbus pin. with this pmos the dev ice can shut off the path between battery and output. during start-up the pmos switch will be opened very slowly by discharg ing his gate with a small current sink. depending on the value of the gate-source capacitance and the start-up time, different current values for the current sink can be programmed. during start-up and operat ion the d cdc also monitors the cu rrent over the sense resistor. if the current limit will be reached during start- up the dcdc will generate an interrupt signal after 5.3usec de-bounce time. if this over-current co ndition is still present aft er 85s the dcdc converter will be shut off by resetting its register. du ring start-up, however, an interrupt will be masked until pin usbh _pg is lower than 1v. figure 27 vbus dcdc block diagram revision 1v3 43 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com vbus charge pump (usb otg supply) with the pin usbh_csn and usbh_csp connected to ground the usb-otg mode is selected. in this mode the charge pump supplies 5v and 8ma. the charge pump uses the qldo2 voltage as input and doubles its voltage with the help of the flying capacitor betwe en cp_cp and cn_gext to its output vbus. if the pulse skip bit is set in the related register, the charge pump switches to pulse s kip mode for improved efficiency. enabled pulse skip mode, however, compromises with a higher output voltage ripple. figure 28 vbus cp block diagram parameter table 34 vbus generation parameter symbol parameter min typ max unit note cp mode i cpout output current 8 ma @ 4.7v output voltage i vdd quiescent current 600 a v cpout output voltage 4.7 5.0 5.3 v c fly =100nf,i cpout =0..8ma f in switching frequency 375 khz c fly external flying capacitor 100 nf ceramic, low esr ca pacitor between cp_cp and cn_gext c store external storage capacitor 1 2.2 uf ceramic, low esr ca pacitor between vbus and vss dcdc mode i vdd quiescent current 140 a pulse skipping mode v rsense_max current limit at r sense 100 mv e.g.: 1a for 0.1 ohm sense res istor i load load current 0 500 ma @ 5v output voltage f in fixed switching frequency 750 khz t min_on minimum on-time 130 ns mdc maximum duty cycle 91 % c out output capacitor 4.7 f ceramic, +/-20% l inductor 10 h use inductors with small c parasitic (<100pf) for high efficiency n sw nmos switch on-resistance of external swi tching transistor max. 1 p sw pmos switch on-resistance of external pmo s transistor as low as possible, because of efficiency r sense current limit sense resistor 100 m e.g.: 1a for 0.1 ohm sense res istor bvdd=3.3v, t a =25c, unless otherwise specified revision 1v3 44 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 29 15v step-up performance characteristics efficiency vs output current 60 65 70 75 80 85 90 95 100 output current [ma] efficiency [%] dcdc stepup 5v usb host supply v in =3.6v 100ma 500ma register description table 35 usb vbus related registers name base offset description pmu vbus 2-wire serial 1ah dcdc and cp c ontrol, vbus comparator settings revision 1v3 45 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3 system functions 9.3.1 system general the system block handles the power up, power down and regulator voltage settings of the afe. power up conditions the chip powers up when on of the following condition is true: ? hi gh signal on the pwr_up pin (>80ms, >1v & >1/3 bvdd) ? ri sing edge on the vbus pin (usb pl ug in: >80ms, bvdd>3v, vbus>4.5v) ? ri sing edge on the chgin pin (charger plug in: >80ms, bvdd>3v, chgin>4.0v) ? ri sing edge on the rtcsup and consequently on rvdd pin (rtcsup > 1.35v, bvdd >3v) ? rtc wa ke-up: the auto wake-up timer is internally connected to the power-up and hibernation control block. to hold the chip in power up mode t he pwr_hold bit in the syst em register (0x20h) is set. power down conditions the chip automatically shuts off if one of the following conditions arises: ? cl earing the pwr_hold bit in system register (0x20h) ? i 2c watchdog power down(no serial reading for >1s, has to be enabled) ? hea rtbeat watchdog via pin hbt(no watchdog reset via hbt pin for > 500ms, has to be enabled) please note, that when using power-up sequence 16 to 25 no power down is performed but a reset puls (86us typ, 60us min) will be performed. ? bvdd drop s below the minimum threshold voltage (<2.7v) ? l do or step down converter output voltage drop below a programmable level (has to be enabled) ? ju nction temperature reaches maximum threshold, set in supervisor register (0x24h) ? hi gh signal on the pwr_up pin for more than (>5.4s, >1v & >1/3 bvdd). with setting sd_time bit in register 24h the time can be doubled. revision 1v3 46 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com start-up sequence the afe offers 25 different power-up sequences. the specific start-up sequence can be selected via vprg1 and vprog2 pin. each p in detects 5 logical input states which shall come from an external resistor divider network. at first, ldo1 (avdd) and ldo2 (dvdd) is powering up. this cannot be influenced with the selection of specific sequences below. ldo1 and ldo2 are necessary for the internal supply of the afe. after power-up sequence selected by pin vprg1, all voltage settings and power on/off conditions of the described regulators can be programmed via the serial interface. table 36 start-up modes dcdc1 dcdc2 dcdc3 dcdc4 dcdc15 ldo3 ldo4 # vprg2 vprg1 cvdd1 cvdd2 cvdd3 vbus vled pvdd1 pvdd2 xres/ pwgd 1 open open 1,2v 3rd 3,3v 2nd 3,3v 1st x x x x 4th 8th 2 open vdd 1,2v 3rd 2,5v 2nd 3,3v 1st x x x x 4th 8th 3 open 150k-vdd 1,2v 3rd 2,5v 2nd x x x 3,3v 1st x 4th 8th 4 open 150k-vss 1,2v 3rd 1,8v 2nd x x x 3,3v 1st x 4th 8th 5 open vss 1,2v 3rd x x x x 3,3v 1st 2,5v 2nd 4th 8th 6 150k-vdd open 1,5v 3rd 3,3v 2nd 3,3v 1st x x x x 4th 8th 7 150k-vdd vdd 1,5v 3rd 2,5v 2nd 3,3v 1st x x x x 4th 8th 8 150k-vdd 150k-vdd 1,5v 3nd 2,5v 2nd x x x 3,3v 1st x 4th 8th 9 150k-vdd 150k-vss 1,5v 3rd 1,8v 2nd x x x 3,3v 1st x 4th 8th 10 150k-vdd vss 1,5v 3rd x x x x 3,3v 1st 2,5v 2nd 4th 8th 11 vdd open 1,8v 3rd 3,3v 2nd 3,3v 1st x x x x 4th 8th 12 vdd vdd 1,8v 3rd 2,5v 2nd 3,3v 1st x x x x 4th 8th 13 vdd 150k-vdd 1,8v 3nd 2,5v 2nd x x x 3,3v 1st x 4th 8th 14 vdd 150k-vss 1,8v 3rd 1,8v 2nd x x x 3,3v 1st x 4th 8th 15 vdd vss 1,8v 3rd x x x x 3,3v 1st 2,5v 2nd 4th 8th 16 vss open 1,2v 1st 1,8v 2nd 3,3v 3rd 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 17 vss vdd 1,2v 1st 1,8v 2nd 3,0v 3rd 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 18 vss 150k-vdd 1,2v 1st 2,5v 2nd 3,3v 3rd 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 19 vss 150k-vss 1,8v 1st 2,5v 2nd 3,3v 3rd 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 20 vss vss 1,8v 1st 3,3 2nd 3,3v 3rd 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 21 150k-vss open 1,2v 3rd 1,8v 2nd 3,3v 1st 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 22 150k-vss vdd 1,2v 3rd 1,8v 2nd 3,0v 1st 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 23 150k-vss 150k-vdd 1,2v 3rd 2,5v 2nd 3,3v 1st 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 24 150k-vss 150k-vss 1,8v 3rd 2,5v 2nd 3,3v 1st 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th 25 150k-vss vss 1,8v 3rd 3,3 2nd 3,3v 1st 5,0v 5th 5ma 5th 3,0v 6th 3,0v 7th * 8th *? in special mode the xres is going high 85us (min 60us) after pwrup key is released x ? means that this regulator is not started with the start-up sequencer but has to be turned on by the 2-wire serial interface when nee ded. revision 1v3 47 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 30 power up timing register description table 37 system related register name base offset description system 2-wire serial 20h watchdog and over-temperature control, power down enable irq_enrd_1 2-wire serial 24h enable/disable wake-up interrupts, set shut-down time irq_enrd_3 2-wire serial 26h enable/disable junction temperature interrupt revision 1v3 48 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3.2 hibernation general hibernation allows shutting down a part or the complete system. hibernation can be terminated by every possible interrupt of the afe. e.g. one can use the rtc for a time triggered wake-up. the interrupt has to be enabled before going to hibernation table 38 hibernation modes modes vprg2 action keepbit ldos dcdcs vbus dcdc15v hib. with default off off off off off cancel hibernation off default default off off hib. with modif settings off off off no change no change cancel hibernation off as before as before no change no change hib. with modif settings on no chan ge no change no change no change 1-15 vdd 150k- vdd open cancel hibernation on no change no change no change no change hib. with default off off off stays on off cancel hibernation off default default default default hib. with modif settings off off off no change off cancel hibernation off as before as before on as before hib. with modif settings on no chan ge no change no change no change 16-25 vss 150k- vss cancel hibernation on no change no change no change no change ?hibernation with default? means that, the voltage of the power supply is determined by vprog1 pin. ?hibernation with modified settings? means, that the voltage of the power supply is controlled by register settings. figure 31 hibernate timing register description table 39 hibernation related register name base offset description pmu hibernate 2-wire serial 17h-6 hibernation control pmu enable 2-wire serial 18h enables writings to extended register 17h-6 revision 1v3 49 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3.3 supervisor general this supervisor function can be used for automatic detection of bvdd brown out or junction over-temperature condition. bvdd supervision the supervision level can be set in 8 steps @ 60mv from 2.74 to 3.16v. if the level is reached an interrupt can be generated. i f bvdd reaches 2.7v the afe shuts down automatically. junction temperature supervision the temperature supervision level can also be set by 5 bits (120 to ?15 o c). if the temperature reaches this level, an interrupt can be generated. the over-temperature shutdown level is always 20 o c higher. power rail monitoring the 4 main regulators have an extra monitor which measures the output voltage of the regulator. this power rail monitors are in dependent from the 10bit adc. to activate these please see related registers. register description table 40 supervisor related register name base offset description supervisor 2-wire serial 21h battery and junction temperature supervision threshold levels irq_enrd_0 2-wire serial 23h enable/disable pvdd/cvdd monitoring interrupt and shutdown irq_enrd_1 2-wire serial 24h enable/disable pvdd/cvdd monitoring interrupt and shutdown irq_enrd_2 2-wire serial 25h enable/disable battery brown out interrupt irq_enrd_3 2-wire serial 26h enable/disable junction temperature interrupt revision 1v3 50 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3.4 interrupt generation general all interrupt sources can get enabled or disabled by corresponding bits in the 5 irq-bytes. by default no interrupt source is e nabled. the xirq output can get configured to be push/pull or open_drain and active_high or active low with 2 bits in irq_enrd_4 register (27h). default state is open drain and active_low. irq source interpretation there are 3 different modules to process interrupt sources: level the irq output is kept active as long as the interrupt source is present and this irq-bit is enabled edge the irq gets active with a high going edge of this source. the irq stays active until the corresponding irq-register gets read. status change the irq gets active when the source-state changes. the change bit and the status can be read to notice which interrupt was the source. the irq stays active until the corresponding interrupt register gets read. de-bouncer there is a de-bounce function implemented for usb and charger. since these 2 signals can be unstable for the phase of plug-in o r unplug, a de-bounce time of 512ms/256ms/128ms can be selected by 2 bits in the irq_enrd_4 register (27h). interrupt sources 18 irq events will activate the xirq pin: ? h eadphone connected ? m icrophone 1 connected ? m icrophone 2 connected ? m icrophone 1 remote control ? m icrophone 2 remote control ? voi ce activation threshold reached ? rtc s ec/min elapsed ? 10 bit adc end of conversion ? i 2s changed ? usb c hanged ? cha rger changed ? end of charge (at 10% of programmed current ) ? bat tery temperature high (at 42c and 45c with 100k ntc) ? rvdd lo w (e.g. after battery was changed) ? ba ttery low (brown-out voltage reached) ? wa ke-up from hibernation ? po wer-up key (pin pwrup) pressed ? p ower rail monitor: pvdd 1, pvdd2, cvdd1, cvdd2 revision 1v3 51 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3.5 real time clock general the real time clock block is an independent block, which is still working even when the chip is shut down. the only condition f or this operation is that bvddr has a voltage of a bove 1.0v. the block uses a standard 32khz cr ystal that is connected to a low power oscillator. the total power consumption is typ. 12a. (q32k clock buffer not operating) the rtc seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. the rtc can deliver a seconds or m i nutes interrupt. another 23bit wide counter allows auto wake-up (max. after 96 days). this counter is internally connected to the power-up and h ib ernation control block. the rtc voltage regulator (rvdd) further supplies a 128bit sram. it can be used to store settings or data before shutdown. clock adjustment the rtc clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32khz crystals. the nominal frequency shall be 32.768hz. this frequency is divided down to 0.25hz: f = 32.768 / (4*32*1024) at the input of this divider one can add corrective counts, which allow to correct an inaccurate crystal in a range from ?64 co unts (=- 488ppm) to +63 counts (=+480ppm): f corrected = f crystal / [(4*32*1024)-64+rtc_tbc] register description table 41 rtc related register name base offset description rtcv 2-wire serial 28h rtc oscillator and counter enable rtct 2-wire serial 29h rtc interrupt and time correction settings rtc_0 to rtc_3 2-wire serial 2ah to 2dh rtc time-base seconds registers rtc_wakeup 2-wire serial 19h rtc wake-up settings and sdram access irq_enrd_2 2-wire serial 25h interrupt settings for rvdd under-voltage detection irq_enrd_4 2-wire serial 27h interrupt settings for getting a second or minute interrupt revision 1v3 52 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3.6 10-bit adc general this general purpose adc can be used for measuring several voltages and currents to perform functions like battery monitor, tem perature supervision, button press detection, etc.. input sources table 42 adc10 input sources nr. source range lsb description 0 chgout 5.120v 5mv check battery voltage of 4v liio accumulator 1 bvddr 5.120v 5mv check rtc backup batter y v oltage (connected to bvdd inside the package) 2 5.120v 5mv source defined by dc_test in register 0x18 3 chgin 5.120v 5mv check charger input voltage 4 vbus 5.120v 5mv check usb input voltage 5 battemp 2.560v 2.5mv check battery charging temperature 6 mic1s 2.560v 2.5mv check voltage on mic1s for remote control or external voltage m easurement 7 mic2s 2.560v 2.5mv check voltage on mic1s for remote control or external voltage m easurement 8 vbe_1ua 1.024 1mv measuring basis-emitter voltage of temperature sense transistor; tj = 0.5*[adc_bit0:bit9] ? 565/2 9 vbe_2ua 1.024 1mv measuring basis-emitter voltage of temperature sense transistor; tj = 0.5*[adc_bit0:bit9] ? 575/2 10 i_mic1s 1.024ma typ. 2.0ua check current of mic1s for remote control detection 11 i_mic2s 1.024ma typ. 2.0ua check current of mic2s for remote control detection 12 rvdd 2.560v 2.5mv check rtc supply voltage 13..15 reserved 1.024v 1mv for testing purpose only reference avdd=2.9v is used as reference to the adc. avdd is trimmed to +/-20mv with over all precision of +/-29mv. so the absolute accur acy is +/-1%. parameter table 43 adc10 parameter symbol parameter min typ max unit notes r div input divider resistance 138k 180k 234k chgout, bvddr, vbus, chgin adc fs adc full scale range 2.534 2.56 2.586 v ratio1 division factor 1 0.198 0.2 0.202 1 chgout, bvddr, vbus, chgin ratio2 division factor 2 0.396 0.4 0.404 1 rvdd, battemp, mic1s, mic2s gain adc gain stage 2.475 2.5 2.525 v t con conversion time - 34 50 s i_mic fs i_mics full scale range 0.7 1.0 1.4 ma bvdd=3.6v; t amb =25oc; unless otherwise specified register description table 44 adc10 related register name base offset description adc_0 2-wire serial 2eh adc source selection, adc result<9:8> adc_1 2 wire serial 2fh adc result <7:0> irq_enrd_4 2-wire serial 27h interrupt settings for end of conversion interrupt pmu_enable 2-wire serial 18h extended adc source selection revision 1v3 53 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.3.7 unique id code (64 bit otp rom) general this fuse array is used to store a unique identification number, which can be used for drm issues. the number is generated and programmed during the production process. register description table 45 uid related register name base offset description uid_0 to uid_7 2-wire serial 38h to 3fh unique id register 0 to 7 revision 1v3 54 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 9.4 register description table 46 i2c register overview addr name d<7> d<6> d<5> d<4> d<3> d<2> d<1> d<0> lo1_mux_b 0:sum_stereo;1:sum_mdiff 2:adc_in; 3:dac_out - lo1r_vol gain from mux_b to lout1r= (-40.5db ? +6db) 00h line_out1_r 0 0 0 0 0 0 0 0 - mute_off _j - lo1l_vol gain from mux_b to lout1l= (-40.5db ? +6db) 01h line_out1_l 0 0 0 0 0 0 0 0 hp_ovc_to 0: 256ms; 1: 128ms 2: 512ms; (3: 0ms) dac_ direct hpr_vol gain from mux_c to hpr= (-45.43db ? +1.07db) 02h hph_out_r 0 0 0 0 0 0 0 0 mute_on_ k hp_on hpdet_on hpl_vol gain from mux_c to hpl= (-45.43db ? +1.07db) 03h hph_out_l 0 0 0 0 0 0 0 0 lo2_mux_d 0: mic1; 2: mic2 1:mic1_mdiff; 3: stereo_mic - lo2r_vol gain from mux_d to lout2r= (-40.5db ? +6db) 04h line_out2_r 0 0 0 0 0 0 0 0 - mute_off _l - lo2l_vol gain from mux_d to lout2l= (-40.5db ? +6db) 05h line_out2_l 0 0 0 0 0 0 0 0 mic1_agc _off pre1_gain 0: 28db; 1: 34db 2: 40db m1r_vol gain from micamp (n6) to mixer (n15) = (-40.5db ? +6.0db) 06h mic1_r 0 0 0 0 0 0 0 0 m1sup _off mute_off _e rdet1_ off m1l_vol gain from micamp (n6) to mixer (n14) = (-40.5db ? +6.0db) 07h mic1_l 0 0 0 0 0 0 0 0 mic2_agc _off pre2_gain 0: 28db; 1: 34db 2: 40db m2r_vol gain from micamp (n4) to mixer (n12) = (-40.5db ? +6.0db) 08h mic2_r 0 0 0 0 0 0 0 0 m2sup _off mute_off _d rdet2_ off m2l_vol gain from micamp (n4) to mixe r_in (n13)= (-40.5db ? +6.0db) 09h mic2_l 0 0 0 0 0 0 0 0 - - mute_off _b li1r_vol gain from lin1r to mixer (n10)= (-34.5db ? +12db) 0ah line_in1_r 0 0 0 0 0 0 0 0 li1_mode 00: se_sterep; 01: monodiff 10: se_mono mute_off _g li1l_vol gain from lin1l to mixer (n17)= (-34.5db ? +12db) 0bh line_in1_l 0 0 0 0 0 0 0 0 - - mute_off _c li2r_vol gain from lin2r to mixer (n11)= (-34.5db ? +12db) 0ch line_in2_r 0 0 0 0 0 0 0 0 li2_mode 00: se_sterep; 01: monodiff 10: se_mono mute_off _f li2l_vol gain from lin2l to mixer (n16)= (-34.5db ? +12db) 0dh line_in2_l 0 0 0 0 0 0 0 0 - - - dar_vol gain from dac (n19) to mixer/mux (n23)= (-40.5db ? +6db) 0eh dac_r 0 0 0 0 0 0 0 0 - mute_off _h - dal_vol gain from dac (n22) to mixe r/mux (n26) = (-40.5db ? +6db) 0fh dac_l 0 0 0 0 0 0 0 0 adc_mux_a 0: stereo_mic; 1:linein_1 2: linein_2; 3: audiosum - adr_vol gain from mux_a to adc (n9) = (-34.5db ? +12db) 10h adc_r 0 0 0 0 0 0 0 0 revision 1v3 55 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com addr name d<7> d<6> d<5> d<4> d<3> d<2> d<1> d<0> - mute_off _a - adl_vol gain from mux_a to adc (n18) = (-34.5db ? +12db) 11h adc_l 0 0 0 0 0 0 0 0 drive_pwgd 0: 12ma od; 1: 12ma pp 2: 4ma pp; 3: 2ma pp mux_pwgd 0: pwgd; 1: pwm 2: spdif; 3: pll clock drive_q32k 0: 12ma pp; 1: 12ma od 2: 4ma pp; 3: 2ma pp mux_q32k 0: q32k; 1: pwm 2: spdif; 3: pll clock 12h-1 outcontr1 0 0 0 0 0 0 0 0 drive_q24m 0: 12ma pp; 1: 12ma od 2: 4ma pp; 3: 2ma pp mux_q24m 0: q24 1: pll clock spdif_ copy_ok spdif_ mclk_inv spdif_ invalid spdif_cntr 0: off; 1: 32ks 2: 44.1ks; 3: 48ks 12h-2 outcontr2_sp dif 0 0 0 0 0 0 0 0 pwm_ inverted pwm_cycle 0: no pulses; dytycycle = pwm_cycle * 0.3937% 12h-3 pwm 0 0 0 0 0 0 0 0 adc_r_on adc_l_on lout2_on lout1_on lin2_on lin1_on mic2_on mic1_on 14h audioset_1 0 0 0 0 0 0 0 0 bias_off sum_off agc_off ibr_dac dac_on - 15h audioset_2 0 0 0 0 0 0 0 0 lin1mix_o ff lin2mix_o ff mic1mix_o ff mic2mix_o ff dacmix_o ff zcu_off ibr_hph hpcm_on 16h audioset_3 0 0 0 0 0 0 0 0 ldo_pvdd 1_off - prog_ pvdd1 vsel_pvdd1 0h ? fh:1.2v+vsel*50mv (1.2v ? 1.95v) 10h ? 1fh: 2.0v+(vsel-10h)*100mv (2.0v ? 3.5v) 17h-1 pmu pvdd1 0 0 0 0 0 0 0 0 ldo_pvdd 2_off - prog_ pvdd2 vsel_pvdd2 0h ? fh:1.2v+vsel*50mv (1.2v ? 1.95v) 10h ? 1fh: 2.0v+(vsel-10h)*100mv (2.0v ? 3.5v) 17h-2 pmu pvdd2 0 0 0 0 0 0 0 0 skip_off_ cvdd1 prog_ cvdd1 vsel_cvdd1 0h: off; 1h - 38h ?. 0.6v+vsel*50mv ? 0.65v ? 3.40v; (38h ? 3fh ?. 3.4v) 17h-3 pmu cvdd1 0 0 0 0 0 0 0 0 skip_off_ cvdd2 prog_ cvdd2 vsel_cvdd2 0h: off; 1h - 38h ?. 0.6v+vsel*50mv ? 0.65v ? 3.40v; (38h ? 3fh ?. 3.4v) 17h-4 pmu cvdd2 0 0 0 0 0 0 0 0 skip_off_ cvdd3 prog_ cvdd3 vsel_cvdd3 0h: off; 1h - 38h ?. 0.6v+vsel*50mv ? 0.65v ? 3.40v; (38h ? 3fh ?. 3.4v) 17h-5 pmu cvdd3 0 0 0 0 0 0 0 0 - keep_ pvdd2 keep_ pvdd1 keep_ vled keep_ vbus keep_ cvdd3 keep_ cvdd2 keep_ cvdd1 17h-6 pmu hibernate 0 0 0 0 0 0 0 0 - dc_test 0: unused; 1: avdd; 2: dvdd; 3: pvdd1 4: pvdd2; 5: cvdd1; 6; cvdd2; 7: cvdd3 pmu_gate pmu_wr_enable 1: prog 17h-1 / 12h-1 (pvdd1, outcontr1) 2: prog 17h-2 / 12h-2 (pvdd2, outcontr2) 3: prog 17h-3 / 12h-3 (cvdd1, pwm) 4: prog 17h-4 (cvdd2); 5: prog 17h-5 (cvdd3) 6: prog 17h-6 (hibernate); 0,7: unused 18h pmu enable 0 0 0 0 0 0 0 0 1 st write/read: wakeup_byte_1 128s 64s 32s 16s 8s 4s 2s 1s 2 nd write/read: wakeup_byte_2 32ks 16ks 8ks 4ks 2ks 1ks 512s 256s 3 rd wirte/read: wakeup_byte_3 enablewakeup 4k*1ks 2k*1ks 1k*1ks 512ks 256ks 128ks 64ks 19h rtc_wakeup 4 th to 19 th write/read: sram_128 i_pmos_gate 0: 1a; 1: 2a 2: 3a; 3: 4a dcdc_ps_ off dcdc_ pmos_off vbus_comp_th 0: 4.5v; 1: 3.18v 2: 1.5v; 3: 0.6v vbus_skip _on vbus_on 1ah usb_util_dc dc 0 0 0 0 0 0 0 0 dim_up_d own dim_rate 0: no dimming; 1: 150ms 2: 300ms; 3: 500ms i_backlight 0 ? off 1-31 ? led current = 1.25ma*i_backlight (1.25ma ? 38.75ma) 1bh dcdc15 0 0 0 0 0 0 0 0 revision 1v3 56 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com addr name d<7> d<6> d<5> d<4> d<3> d<2> d<1> d<0> please see master clock divider table 1ch i2s 0 0 0 0 0 0 0 0 i2s_maste r_on osc24_pd i2s_ direct q24m_divider 0: /1; 1: /2 2: /4; 3:off pll_mode 0: reserved; 1: 16-48ks 2: 8-12ks; 3: reserved i2s_divide r_8 1dh i2s_pll_osc 0 0 0 0 0 0 0 0 design_version<3:0> heartbea t_on jtemp_ off watchdo g_on pwr_hold 20h system 1 1 1 1 0 0 0 1 bvdd_sup v_brownout = 2..74v+bvdd_sup*60mv (2.74v .. 3.16v) jtemp_sup temp_shutdown = 140c ? jtemp_sup*5c (+140c..?15c) temp_irq = 120c ? jtemp_sup*5c (+120c .. ?35c) 21h supervisor 0 0 1 0 0 0 0 0 bat_temp _off chg_i ichg=50ma+50ma*chg_i (50ma ? 400ma) chg_v vchg=3.9v+50mv*chg_v (3.9v ? 4.25v) chg_off 22h charger 0 0 0 0 0 0 0 0 cvdd2_ en_sd cvdd2_ en_irq cvdd1_ en_sd cvdd1_ en_irq pdd2_ en_sd pdd2_ en_irq pdd1_ en_sd pdd1_ en_irq cvdd2_ under cvdd2_ over cvdd1_ under cvdd1_ over pdd2_ under pdd2_ over pdd1_ under pdd1_ over 23h irq_enrd_0 0 0 0 0 0 0 0 0 pwrup_ irq wakeup_ irq voxm2_ irq voxm1_ irq cvdd3_ en_sd cvdd3_ en_irq sd_time 0: 5.4s 1: 10.9s - cvdd3_ under cvdd3_ over 24h irq_enrd_1 0 0 0 0 0 0 0 0 battemp_ high chg_ eoc chg_ status chg_ changed usb_ status usb_chan ged rvdd_low bvdd_low 25h irq_enrd_2 0 0 0 0 0 0 0 0 jtemp_hi gh - hph_ ovc i2s_ status i2s_ changed mic2_ connect mic1_ connect hph_ connect 26h irq_enrd_3 0 0 0 0 0 0 0 0 t_deb 0: 512ms; 1: 256ms 2: 128ms; 3: 0ms xirq_ah xirq_pp rem2_det rem1_det rtc_ update adc_eoc 27h irq_enrd_4 0 0 0 0 0 0 0 0 v_rvdd v(rvdd)=1v+v_rvdd*0.1v default is 1.2v. - rtc_on osc32_on 28h rtcv 0 0 1 0 0 0 1 1 irq_min trtc<6:0> 29h rtct 0 1 0 0 0 0 0 0 qrtc<7:0> 2ah rtc_0 0 0 0 0 0 0 0 0 qrtc<15:8> 2bh rtc_1 0 0 0 0 0 0 0 0 qrtc<23:16> 2ch rtc_2 0 0 0 0 0 0 0 0 qrtc<31:24> 2dh rtc_3 0 0 0 0 0 0 0 0 adc_source<3:0> 0: chgout; 1: bvddr; 2: dc_test; 3: chg_in; 4: vbus; 5: battemp; 6: msup1; 7: msup2; 8: vbe_1ua; 9: vbe_2ua; 10: i_msup1; 11: i_msup2; 12; rvdd; 13, 14, 15: reserved - - adc<9:8> 2eh adc_0 0 0 0 0 0 0 x x adc<7:0> 2fh adc_1 x x x x x x x x 38-3f uid_0 .. 7 id<7:0> ? id<63:56> revision 1v3 57 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 47 line_out1_r register name base default line_out1_r 2-wire serial 00h right line output 1 register offset: 00h configures mux_b and the audio gain from mux_b output to lout1r output. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 lo1_mux_b 00 r/w multiplexes the analog audio inputs of mux_b to lout1r and at lout1l 00: sum stereo 01: sum mono differential (the gain of lout1r shall be 0db t o hold signals in symmetry) 10: adc (n9/n18) 11 : dac (n23/n26) 5 0 n/a 4:0 lo1r_vol 00000 r/w volume settings for right line output 1, adjustable in 32 steps @ 1.5db; gain from mux_b to lout1r 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 48 line_out1_l register name base default line_out1_l 2-wire serial 00h left line output 1 register offset: 01h configures the audio gain from mux_b output to lout1l output and controls mute switch j this register is reset when the stage is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 0 n/a 6 mute_off_j 0b r/w control of mute switch j 0:line output set to mute 1: normal operation 5 0 n/a 4:0 lo1l_vol 00000 r/w volume settings for left line output 1, adjustable in 32 steps @ 1.5db; gain from mux_b to lout1l 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain revision 1v3 58 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 49 hph_out_r register name base default hph_out_r 2-wire serial 00h right headphone output register offset: 02h configures mux_c and the audio gain from mux_c output to hpr output. this register is reset at a dvdd-por. bit bit name default access bit description 7:6 hp_ovc_to 00 r/w headphone amplifier over current time out. the headphone am plifier is powered down if an over-current is detected. the current thresholds are 150ma at pins hpr / hpl pin or 300ma at pin hpcm (e.g. shorted headphone outputs) 11: 0 ms ( no power down) 10: 512ms 01: 128ms 00: 256 ms 5 dac_direct 0 r/w 0: mux_c output connected to limiter (n24/n25) 1 : mux_c output connected to dac (n23/n26) 4:0 hpr_vol 00000 r/w volume settings for right headphone output, adjustable in 32 st eps @ 1.5db; gain from mux_c to hpr output 11111: 1.07 db gain 11110: -0.43 db gain .. 00001: -43.93 db gain 00000: -45.43 db gain table 50 hph_out_l register name base default hph_out_l 2-wire serial 00h left headphone output register offset: 03h configures the audio gain from mux_c output to hpl output and controls mute switch k this register is reset at a dvdd-por. bit bit name default access bit description 7 mute_on_k 0 r/w control of mute switch k 0: normal operation 1: headphone output set to mute (mute is on during power-up) 6 hp_on 0 r/w 0: headphone stage not powered 1: power up headphone stage 5 hpdet_on 0 r/w enables the detection when a headset gets connected. hpcm i s used as a sense pin and is biased to 150mv 0: no headphone detection 1: enable headphone detection 4:0 hpl_vol 00000 r/w volume settings for left headphone output, adjustable in 32 st eps @ 1.5db; gain from mux_c output to hpl output 11111: 1.07 db gain 11110: -0.43 db gain .. 00001: -43.93 db gain 00000: -45.43 db gain revision 1v3 59 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 51 line_out2_r register name base default line_out2_r 2-wire serial 00h right line output 2 register offset: 04h configures mux_b and the audio gain from mux_b output to lout2r output. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 lo2_mux_d 00 r/w multiplexes the analog audio inputs of mux_d to lout2r and at lout2l 00: mic1 01: mic1 mono differential (the gain of lout2r shall be 0db t o hold signals in symmetry) 10: mic2 11 : stereo mic 5 0 n/a 4:0 lo2r_vol 00000 r/w volume settings for right line output 2, adjustable in 32 steps @ 1.5db; gain from mux_d to lout2r 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 52 line_out2_l register name base default line_out2_l 2-wire serial 00h left line output 2 register offset: 05h configures the audio gain from mux_b output to lout2l output and controls mute switch j this register is reset when the stage is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 0 n/a 6 mute_off_l 0b r/w control of mute switch l 0:line output set to mute 1: normal operation 5 0 n/a 4:0 lo2l_vol 00000 r/w volume settings for left line output 2, adjustable in 32 steps @ 1.5db; gain from mux_d to lout2l 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain revision 1v3 60 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 53 mic1_r register name base default mic1_r 2-wire serial 00h right microphone input 1 register offset: 06h configures the gain from microphone 1 amplifier output up to mixer input ( ). this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 mic1_agc_off 0 r/w control of limiter agc (automatic gain control). limits high d ynamic range of electrete/mems microphone (e.g. user shouts or blows into microphone) 0: automatic gain co ntrol enabled 1: automatic gain control disabled 6:5 pre1_gain 00 r/w sets the gain of the microphone 1 preamplifier (gain from m icrophone inputs to n5) 00: gain set to 28 db 01: gain set to 34 db 10: gain set to 40 db 11: reserved, do not use. 4:0 m1r_vol 00000 r/w volume settings for right microphone input 1, adjustable in 32 st eps @ 1.5db; gain from microphone amplifier (n6) to mixer input (n15) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 54 mic1_l register name base default mic1_l 2-wire serial 00h left microphone input 1 register offset: 07h configures the gain from microphone 1 amplifier output up to mixer input ( ) a nd controls mute switch d. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 m1sup_off 0 r/w 0: microphone 1 supply enabled 1: microphone supply disabled 6 mute_off_e 0 r/w control of mute switch e 0: microphone input 1 set to mute 1: normal operation 5 rdet1_off 0 r/w disables the microphone 1 detect function (30kohm pull-up fr om mic1s to avdd) to use the terminal as adc-10 input 0: microphone 1 detection enabled 1: microphone detection disabled 4:0 m1l_vol 00000 r/w volume settings for left microphone 1 input, adjustable in 32 st eps @ 1.5db; gain from microphone amplifier (n6) to mixer input (n14) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain revision 1v3 61 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 55 mic2_r register name base default mic2_r 2-wire serial 00h right microphone input 2 register offset: 08h configures the gain from microphone 2 amplifier output up to mixer input ( ). this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 mic2_agc_off 0 r/w control of limiter agc (automatic gain control). limits high d ynamic range of electrete/mems microphone (e.g. user shouts or blows into microphone) 0: automatic gain co ntrol enabled 1: automatic gain control disabled 6:5 pre2_gain 00 r/w sets the gain of the microphone 2 preamplifier (gain from m icrophone inputs to n5) 00: gain set to 28 db 01: gain set to 34 db 10: gain set to 40 db 11: reserved, do not use. 4:0 m2r_vol 00000 r/w volume settings for right microphone input 2, adjustable in 32 st eps @ 1.5db; gain from microphone amplifier (n4) to mixer input (n12) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 56 mic2_l register name base default mic2_l 2-wire serial 00h left microphone input 2 register offset: 09h configures the gain from microphone 2 amplifier output up to mixer input ( ) a nd controls mute switch e. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 m1sup_off 0 r/w 0: microphone 2 supply enabled 1: microphone supply disabled 6 mute_off_d 0 r/w control of mute switch d 0: microphone input 2 set to mute 1: normal operation 5 rdet2_off 0 r/w disables the microphone 2 detect function (30kohm pull-up fr om mic1s to avdd) to use the terminal as adc-10 input 0: microphone 1 detection enabled 1: microphone detection disabled 4:0 m2l_vol 00000 r/w volume settings for left microphone 2 input, adjustable in 32 st eps @ 1.5db; gain from microphone amplifier (n4) to mixer input (n13) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain revision 1v3 62 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 57 line_in1_r register name base default line_in1_r 2-wire serial 00h right line input 1 registers offset: 0ah configures the gain from analog line input pin lin1r to mixer input ( ) a nd controls mute switch b. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 00 n/a 5 mute_off_b 0 r/w control of mute switch b 0: right line input is set to mute 1: normal operation 4:0 li1r_vol 00000 r/w volume settings for right line input 1, adjustable in 32 steps @ 1 .5db; gain from line input pin (lin1r) to mixer input (n10) 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain table 58 line_in1_l register name base default line_in1_l 2-wire serial 00h left line input 1 registers offset: 0bh configures the gain from analog line input pin lin1l to mixer input ( ) a nd controls mute switch g. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 li1_mode 00 r/w configures line input 1 (right and left channel) in accordance wi th the connected input sources 00: inputs switched to single ended stereo 01: inputs switched to differential mono 10: inputs switched to single ended mono 11: reserved, do not use. 5 mute_off_g 0 r/w control of mute switch g 0: left line input is set to mute 1: normal operation 4:0 li1l_vol 00000 r/w volume settings for right line input 1, adjustable in 32 steps @ 1 .5db; gain from line input pin (lin1l) to mixer input (n17) 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain revision 1v3 63 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 59 line_in2_r register name base default line_in2_r 2-wire serial 00h right line input 2 register offset: 0ch configures the gain from analog line input pin lin2r to mixer input ( ) a nd controls mute switch c. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 00 n/a 5 mute_off_c 0 r/w control of mute switch c 0: right line input is set to mute 1: normal operation 4:0 li2r_vol 00000 r/w volume settings for right line input, adjustable in 32 steps @ 1 .5db; gain from line input pin (lin2r) to mixer input (n11) 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain table 60 line_in2_l register name base default line_in2_l 2-wire serial 00h left line input 2 registers offset: 0dh configures the gain from analog line input pin lin2l to mixer input ( ) a nd controls mute switch f. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 li2_mode 00 r/w configures line input 2 (right and left channel) in accordance wi th the connected input sources 00: inputs switched to single ended stereo 01: inputs switched to differential mono 10: inputs switched to single ended mono 11: reserved, do not use. 5 mute_off_f 0 r/w control of mute switch f 0: left line input is set to mute 1: normal operation 4:0 li2l_vol 00000 r/w volume settings for right line input, adjustable in 32 steps @ 1 .5db; gain from line input pin (lin2l) to mixer input (n16) 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain revision 1v3 64 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 61 dac_r register name base default dac_r 2-wire serial 00h right dac output registers offset: 0eh configures the gain from dac output to mixer input ( ) / mux input. this register is reset when the block is disabled in audioset2 register (15h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:5 000 n/a 4:0 dar_vol 00000 r/w volume settings for right dac output, adjustable in 32 steps @ 1 .5db; gain from dac output (n19) to mixer/mux input (n23). 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 62 dac_l register name base default dac_l 2-wire serial 00h left dac output registers offset: 0fh configures the gain from dac output to mixer input ( ) / mux input and controls mute switch h. this register is reset when the block is disabled in audioset2 register (15h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 0 n/a 6 mute_off_h 0 r/w control of mute switch h 0: dac output is set to mute 1: normal operation 5 0 n/a 4:0 dal_vol 00000 r/w volume settings for left dac output, adjustable in 32 steps @ 1 .5db: gain from dac output (n22) to mixer/mux input (n26). 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain revision 1v3 65 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 63 adc_r register name base default adc_r 2-wire serial 00h right adc input registers offset: 10h configures mux_a and the gain from mux_a output to the adc input this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 adc_mux_a 00 r/w connect mux a output to following inputs 00: microphone (n4/n6) 01: line_in1 (n1/n8) 10: line_in2 (n2/n7) 11: audio sum (n24/n25) 5 0 n/a 4:0 adr_vol 00000 r/w volume settings for right adc input, adjustable in 32 steps @ 1 .5db; gain from mux_a output to adc input (n9). 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain table 64 adc_l register name base default adc_l 2-wire serial 00h left adc input registers offset: 11h configures the gain from mux_a output to the adc input and controls mute switch a. this register is reset when the block is disabled in audioset1 register (14h) or at a dvdd-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 0 n/a 6 mute_off_a 0 r/w control of mute switch a 0: adc input is set to mute 1: normal operation 5 0 n/a 4:0 adl_vol 00000 r/w volume settings for left adc input, adjustable in 32 steps @ 1 .5db, gain from mux_a output to adc input (n18). 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain revision 1v3 66 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 65 output control register name base default outcontr1 2-wire serial 00h q32k and pwgd output control register offset: 12h-1 configures pwgd pin (power good) and q32k pin (output of 32khz oscillator). this is an extended register and needs to be enabled by writing 001b to reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7:6 drive_pwgd 00 r/w enables the pwgd output pin either to open-drain or push-pull a nd sets various driving strengths 00: 12ma push-pull output 0 1: 12ma open-drain output 10: 4ma push-pull output 11: 2ma push-pull output 5:4 mux_pwgd 00 r/w multiplexes various digital signals to the pwgd output pin 00: powergood control signal 0 1: pwm signal to dim leds etc. 10: spdif converted from sdi to dac 11: pll output clock 3:2 drive_q32k 00 r/w enables the q32k output pin either to open-drain or push-pull a nd sets various driving strengths 00: 12ma push-pull output 0 1: 12ma open-drain output 10: 4ma push-pull output 11: 2ma push-pull output 1:0 mux_q32k 00 r/w multiplexes various digital signals to the q32k output pin 00: 32khz r tc clock 01: pwm signal to dim leds etc. 10: spdif converted from sdi to dac 11: pll output clock revision 1v3 67 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 66 spdif register name base default outcontr2_spdif 2-wire serial 00h spdif and q24m output control register offset: 12h-2 adds status bits to the spdif bit-stream, configures the spdif output and the q24m p in (output of 24mhz oscillator) this is an extended register and needs to be enabled by writing 010b to reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7:6 drive_q24m 00 r/w enables the q24m output pin either to open-drain or push-pull a nd sets various driving strengths 00: 12ma push-pull output 0 1: 12ma open-drain output 10: 4ma push-pull output 11: 2ma push-pull output 5 mux_q24m 0 r/w multiplexes various digital signals to the q24m output pin 0: 24mhz oscillator clock 1: pll output clock 4 spdif_copy_ok 0 spdif copy control bit 0: copy not permitted 1: copy permitted 3 spdif_mclk_inv 0 spdif master clock control bit 0: master clock 1 : master clock inverted 2 spdif_invalid 0 spdif sample status bit 0: sample valid 1: sample invalid 1:0 spdif_cntr 00 r/w spdif output on/off control and sample rate status bits 00: spdif output off 01 : spdif output on (32ks) 10: spdif output on (44.1ks) 11: spdif output on (48ks) revision 1v3 68 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 67 pwm register name base default pwm 2-wire serial 00h pwm output control register offset: 12h-3 sets the pwm output duty cycle and signal polarity. this is an extended register and needs to be enabled by writing 011b to reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7 pwm_inverted 0 r/w pwm output polarity 0: not inverted 1: inverted 6:0 pwm_cycle 0000000 r/w sets the pwm duty cycle duty cycle = pwm_cycle * 0.3937% pw m_cycle = 0 means no pulse table 68 audioset_1 register name base default audioset_1 2-wire serial 00h first audio set register offset: 14h powers the various audio inputs and outputs up or down. attent ion: this control register resets and holds microphone, line out, and adc related registers in reset. after activation the required register settings need to be re- programmed. this register is reset at a dvdd-por. bit bit name default access bit description 7 adc_r_on 0 r/w 0: adc right chan nel power ed down 1: adc right channel enabled for recording 6 adc_l_on 0 r/w 0: adc left channel powered down 1: adc left channel enabled for recording 5 lout2_on 0 r/w 0: line output 2 powered down 1: line output enabled 4 lout1_on 0 r/w 0: line output 1 powered down 1: line output enabled 3 lin2_on 0 r/w 0: line input 2 powered down 1: line input 2 enabled 2 lin1_on 0 r/w 0: line input 1 powered down 1: line input 1 enabled 1 mic2_on 0 r/w 0: microphone input 2 powered down 1: microphone input 1 enabled 0 mic1_on 0 r/w 0: microphone input 1 powered down 1: microphone input 1 enabled revision 1v3 69 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 69 audioset_2 register name base default audioset_2 2-wire serial 00h second audio set register offset: 15h powers various internal audio blocks up or down and controls bias current. attention: th is control register resets and holds dac related registers in reset. after activation the required register settings need to be re-programmed. this register is reset at a dvdd-por. bit bit name default access bit description 7 bias_off 0 r/w power-down of the agnd bias. this bit can be set, if the afe i s used for digital data transfer and pmu functions only and all the analog audio blocks are not used. 0: bias enabled 1: bias disabled, for power saving in non audio mode 6 sum_off 0 r/w power-down of r an d l 0: mixer stage enabled (limits output signal to 1vp) 1: mixer stage powered down 5 agc_off 0 r/w switches the signal limiter off (n20/n21) 0: automatic gain co ntrol for summin g stage enabled 1: automatic gain control for summing stage disabled 4:3 ibr_dac<1:0> 00 r/w bias current settings for dac: 00: 50% 01: 60% 10: 75% 11: 100% 2 dac_on 0 r/w 0: dac powered down 1: dac enabled 1:0 revision 1v3 70 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 70 audioset_3 register name base default audioset_3 2-wire serial 00h third audio set register offset: 16h sets headphone output bias currents and operation modes and enables audio signal i nputs to r and l. this register is reset at a dvdd-por. bit bit name default access bit description 7 lin1mix_off 0 r/w input from line input 1 to r and l 0: on 1: off 6 lin2mix_off 0 r/w input from line input 2 to r and l 0: on 1: off 5 mic1mix_off 0 r/w input from microphone 1 to r an d l 0: on 1: off 4 mic2mix_off 0 r/w input from microphone 2 to r an d l 0: on 1: off 3 dacmix_off 0 r/w input from dac to r a nd l 0: on 1: off 2 zcu_off 0 r/w zero cross gain update of audio outputs. audio gain settings ch anges will only be executed when the signal level is close to zero 0: zero cross update enabled 1: zero cross update disabled 1 ibr_hph 0 r/w bias current increase for the headphone amplifier depending on load conditions 0: 100% 1: 150% 0 hpcm_on 0 r/w power-up of the headphone common mode buffer: 0: headphone cm buffer is switched off 1: headphone cm buffer is switched on revision 1v3 71 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 71 pmu pvdd1 register name base default pmu pvdd1 2-wire serial 00h pvdd1 low drop-out regulator (ldo3) control register offset: 17h-1 this is an extended register and needs to be enabled by writing 001b to reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7 ldo_pvdd1_off 0 r/w power-down of ldo for pvdd1 0: pvdd1 (ldo3) enable 1: pvdd1 ( ldo3) power-down 6 0 n/a 5 prog_pvdd1 0 r/w enables settings either selected by external pins (vprgx) or se ttings stored in the 17h-1 register 0: vprgx pins controlled 1 : register controlled 4:0 vsel_pvdd1 00000 r/w the voltage select bits set the ldo output in 2 different re solution ranges range: 00h until 0fh in 50mv steps pvdd 1=1.2v+vsel_pvdd1*50mv ( 1.2v until 1.95v) range: 10h until 1fh in 100mv steps pvdd 1=2.0v+vsel_pvdd1*100mv (2.0v until 3.5v) table 72 pmu pvdd2 register name base default pmu pvdd2 2-wire serial 00h pvdd2 low drop-out regulator (ldo4) control register offset: 17h-2 this is an extended register and needs to be enabled by writing 010b to reg. 18h first. this register is reset at a dvdd-por. bit bit name default access bit description 7 ldo_pvdd2_off 0 r/w power-down of ldo for pvdd2 0: pvdd2 (ldo4) enable 1: pvdd2 ( ldo4) power-down 6 0 n/a 5 prog_pvdd2 0 r/w enables settings either selected by external pin (vprgx) or se ttings stored in the 17h-2 register 0: vprgx pins controlled 1 : register controlled 4:0 vsel_pvdd2 00000 r/w the voltage select bits set the ldo output in 2 different re solution ranges range: 00h until 0fh in 50mv steps pvdd 2=1.2v+vsel_pvdd1*50mv ( 1.2v until 1.95v) range: 10h until 1fh in 100mv steps pvdd 2=2.0v+vsel_pvdd1*100mv (2.0v until 3.5v) revision 1v3 72 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 73 pmu cvdd1 register name base default pmu cvdd1 2-wire serial 00h cvdd1 dc/dc buck regulator control register offset: 17h-3 this is an extended register and needs to be enabled by writing 011b to reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7 skip_off_cvdd1 0 r/w disables pulse skip mode 0: 170ma current force / pulse skip mode enabled 1 : current force / pulse skip mode disabled (only on without load) 6 prog_cvdd1 0 r/w enables settings either selected by external pin (vprgx) or se ttings stored in the 17h-3 register 0: vprgx pins controlled 1 : register controlled 5:0 vsel_cvdd1 00000 r/w the voltage select bits set the dc/dc output voltage level and po wer the dc/dc converter down. 00000: dc/dc powered down 01h until 38h in 50mv steps cvdd1=0. 6v+vsel_cvdd1*50mv (0.65v until 3.4v) 38h until 3fh = 3.4v (no change) table 74 pmu cvdd2 register name base default pmu cvdd2 2-wire serial 0x00 cvdd2 dc/dc buck regulator control register offset: 17h-4 this is an extended register and needs to be enabled by writing 100bto reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7 skip_off_cvdd2 0 r/w disables pulse skip mode 0: 170ma current force / pulse skip mode enabled 1 : current force / pulse skip mode disabled (only on without load) 6 prog_cvdd2 0 r/w enables settings either selected by external pin (vprgx) or se ttings stored in the 17h-4 register 0: vprgx pins controlled 1 : register controlled 5:0 vsel_cvdd2 00000 r/w the voltage select bits set the dc/dc output voltage level and po wer the dc/dc converter down. 00000: dc/dc powered down 01h until 38h in 50mv steps cvdd2=0. 6v+vsel_cvdd1*50mv (0.65v until 3.4v) 38h until 3fh = 3.4v (no change) revision 1v3 73 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 75 pmu cvdd3 register name base default pmu cvdd3 2-wire serial 0x00 cvdd3 dc/dc buck regulator control register offset: 17h-5 this is an extended register and needs to be enabled by writing 101bto reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7 skip_off_cvdd3 0 r/w disables pulse skip mode 0: 170ma current force / pulse skip mode enabled 1 : current force / pulse skip mode disabled (only on without load) 6 prog_cvdd3 0 r/w enables settings either selected by external pin (vprgx) or se ttings stored in the 17h-5 register 0: vprgx pins controlled 1 : register controlled 5:0 vsel_cvdd3 00000 r/w the voltage select bits set the dc/dc output voltage level and po wer the dc/dc converter down. 00000: dc/dc powered down 01h until 38h in 50mv steps cvdd2=0. 6v+vsel_cvdd1*50mv (0.65v until 3.4v) 38h until 3fh = 3.4v (no change) table 76 pmu hibernate register name base default pmu hibernate 2-wire serial 00h pmu hibernation control regist er (pvdd1/2, cvdd1/2/3, vled) offset: 17h-6 hibernation is started when writing to this register. this is an extended register and needs to be enabled by writing 110b to reg. 18h first. thi s register is reset at a dvdd-por. bit bit name default access bit description 7 0 n/a 6 keep_pvdd2 0 r/w keeps the programm ed pvdd 2 level during hibernation 0: power down pvdd2 1 : keep pvdd2 5 keep_pvdd1 0 r/w keeps the programm ed pvdd 1 level during hibernation 0: power down pvdd1 1 : keep pvdd1 4 keep_vled 0 r/w keeps the 15v dc/dc st ep-up for backlight sw itched on 0: power down cvdd1 1 : keep cvdd1 3 keep_vbus 0 r/w keeps the programm ed vbu s level during hibernation 0: power down cvdd2 1 : keep cvdd2 2 keep_cvdd3 0 r/w keeps the programm ed cvdd3 level during hibernation 0: power down cvdd3 1 : keep cvdd3 1 keep_cvdd2 0 r/w keeps the programm ed cvdd2 level during hibernation 0: power down cvdd2 1 : keep cvdd2 0 keep_cvdd1 0 r/w keeps the programm ed cvdd1 level during hibernation 0: power down cvdd1 1 : keep cvdd1 revision 1v3 74 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 77 pmu enable register name base default pmu enable 2-wire serial 00h pmu extension enable register offset: 18h enables 12h and 17h to write into extended registers and allows multiplexing supply vo ltages for monitoring via adc10. this register is reset at a dvdd-por. bit bit name default access bit description 7 0 n/a 6:4 dc_test 000 r/w allows multiplexing internal and external supply voltages to o ne dc test node which can be further multiplexed to adc10. the accuracy is 5mv/lsb (see reg. 2eh) 000: not used 0 01: avdd 010: dvdd 011: pvdd1 100: pvdd2 101: cvdd1 110: cvdd2 111: cvdd3 3 pmu_gate 0 r/w enables all settings made in registers 0x17-x at once. if this b it is set, changes are activated as soon as they are written to the related register. 0: no change 1 : change at once 0:2 pmu_wr_enable 000 r/w enables extended registers 12h-x and 17h-x 000: not used 001: enables 17h-1 for pvdd1 settings e nables 12h-1 for outcntr1 settings 010: enables 17h-2 for pvdd2 settings e nables 12h-2 for outcntr2_spdif settings 011: enables 17h-3 for cvdd1 settings e nables 12h-3 for pwm settings 100: enables 17h-4 for cvdd2 settings 10 1: enables 17h-5 for cvdd3 settings 110: enables 17h-6 for hibernation settings 111: not used revision 1v3 75 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 78 rtc_wakeup register name base default rtc_wakeup 2-wire serial n/a rtc wake-up and sram register offset: 19h sets and enables the rtc wake-up counter and programs the 128bit sram. 3 bytes n eed to be written in a sequence to set the counter. the 3-byte sequence allows to set the counter to every value between 1sec and 8388608sec (=97 days). the msb of the 3 rd byte enables the wake-up counter. byte 4 ?19 will program the static 128bit sram which is supplied by rvdd. this register is reset at a rvdd-por. adr. byte name default access bit description 7:0 wake_up_byte0 (1 st write to 0x19 is byte 0) 00h r/w 0000 0001: 1sec 0 000 0010: 2sec 0000 0100: 4sec 0000 1000: 8sec 0001 0000: 16sec 0010 0000: 32sec 0100 0000: 64sec 1000 0000: 128sec 7:0 wake_up_byte1 (2 nd write to 0x19 is byte 1) 00h r/w 0000 0001: 256sec 0 000 0010: 512sec 0000 0100: 1 024sec 0000 1000: 2 048sec 0001 0000: 4 096sec 0010 0000: 8 192sec 0100 0000: 16 384sec 1000 0000: 32 768sec 7:0 wake_up_byte2 (3 rd write to 0x19 is byte 2) 00h r/w 000 0001: 65 536sec 000 0010: 131 072sec 000 0100: 262 144sec 000 1000: 524 288sec 001 0000: 1 048 576sec 010 0000: 2 097 152sec 100 0000: 4 194 304sec 0xxx xxxxxb = wake-up disabled 1 xxx xxxxxb = wake-up enabled 7:0 sram_128 (4 th ? 19 th write to 0x19 programs the 128bit static sram) 00000000 r/w xxxx xxxxb = byte 4 : xxxx xxxxb = byte 19 revision 1v3 76 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 79 usb_util register name base default usb_util_dcdc 2-wire serial 00h usb utility register offset: 1ah controls vbus output voltage and the external transistor as well as special mode bits for the dcdc step-d own converters this register is reset at a dvdd-por. bit bit name default access bit description 7:6 i_pmos_gate 00 r/w sets the gate current level into the external pmos transistor to co ntrol the inrush current to vbus 00: 1a 01: 2a 10: 3a 11: 4a 5 dcdc_ps_off 0 r/w dis ables 200ua power sa ving in skip mode 0: power savings on 1: power savings off 4 dcdc_pmos_off 0 r/w disables the pmos of dcdc step down 1, 2 and 3 to be switched fully on, if the regulator cannot achieve the programmed output voltage anymore. 0: pmos fully on 1: pmos switching 3:2 vbus_comp_th 00 r/w sets the threshold for the vbus comparator. the output can b e read in register 25h. 00: 4.5v 01: 3.18v 10: 1.5v 11: 0.6v 1 vbus_skip_on 0 r/w enables the skip mode for the vbus 1:2 charge pump which i ncreases efficiency for small loads connected to vbus supply, but increases vbus supply ripple 0 vbus_on 0 r/w switches the vbus output voltage on and off 0: vbus output voltage disabled 1: vbus output voltage enabled revision 1v3 77 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 80 dcdc15 register name base default dcdc15 2-wire serial 00h 15v dcdc step-up control register offset: 1bh controls the back-light current and back-light dim rate. this register is reset at a dvdd-por. bit bit name default access bit description 7 dim_up_down 0 r/w starts dimming up/down or switches led back-light on/off when dim_rate = 00b 0: dim down 1: dim up 6:5 dim_rate 00 r/w sets the dim rate of the led back-light current from 0ma to i_ backlight and vice versa 00: no dimming (immediate on/off) 0 1: 150ms 10: 300ms 11: 500ms 4:0 i_backlight 00000 r/w sets the current into pin isink in 1.25ma steps (internal cu rrent source to control led backlight current). setting 11111b enables the voltage feedback mode to supply e.g. oleds with a constant voltage supply. 00000: dcdc15 switched off 00001: 1.25ma 00010: 2.5ma .. 11110: 37.5ma 11111: 38.75ma table 81 i2s register name base default i2s 2-wire serial 00h i2s mode control register (master mode only) offset: 1ch contains lower 8 bits for i2s master mode clock generation divider. this register is reset at a dvdd-por. bit bit name default access bit description 7:0 i2s_divider 00h r/w please see master clock divider table revision 1v3 78 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 82 i2s_pll_osc register name base default i2s_pll_osc 2-wire serial 00h i2s, pll and oscillator mode control registers offset: 1dh this register is reset at a dvdd-por. bit bit name default access bit description 7 i2s_master_on 0 r/w switc hed the i2s master mode on 0: i2s slave mode operation 1: i2s master mode 6 osc24_pd 0 r/w powers the 12-24mhz oscillator down. for operation a 12- 24 mhz crystal needs to be connected to pins xin24/xout24. 0: 12-24mhz oscillator enabled 1: powered down 5 i2s_direct 0 r/w switches the pwgd pin to an input for an external master c lock (e.g. coming form the cpu). this bit overwrites prior setting for the pwgd pin. only valid fro i2s slave mode operation. 0: disabled 1: enabled 4:3 q24m_divider 00 r/w sets the divider for q24m clock output or powers q24m clock o utput buffer down 00: divide by 1 01 :divide by 2 10:divide by 4 11: off 2:1 pll_mode 00 r/w preset of pll bias for the following sampling frequencies 00: reserved 01 :16-48ks 10: 8-12ks 11: reserved 0 i2s_divider_8 0 r/w bit 8 of i2s_divider (reg. 1ch) please see master clock divider table revision 1v3 79 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 83 system register name base default system 2-wire serial e1h system settings register offset: 20h controls the powering down conditions of the afe. the ic can also be emergency shut d own by a high level for 5.4sec (or 10.9sec see reg. 24h) at the pwrup input pin this register is reset at a dvdd-por. bit bit name default access bit description 7:4 version <3:0> 1111 r afe number to identify the design version 1111: revision 7 3 heartbeat_on 0 r/w heartbeat (hbt) watchdog the watchdog counter will be reset by a rising edge at the hbt i nput pin which has to occur at least every 500ms. if the watchdog counter is not reset, the afe will be powered down. when start-up sequence #16-#25 is selected, no power down i s performed but a reset invoked via the xres output pin (pulse duration = 86s typ., 60s min) 0: hbt watchdog is disabled 1: hbt watchdog is enabled 2 jtemp_off 0 r/w junction temperature supervision (level can be set in register 21 h) 0: temperature supervision enabled 1: temperature supervision disabled 1 watchdog_on 0 r/w 2-wire serial interface watchdog to reset the watchdog counter a 2-wire serial read operation has to be performed at least every 500ms. if the watchdog counter is not reset, the afe will be powered down. 0: watchdog is disabled 1: watchdog is enabled 0 pwr_hold 1 r/w 0: power up hold is cleared and afe is powered down 1: set to on after power on revision 1v3 80 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 84 supervisor register name base default supervisor 2-wire serial 00h supervisor register offset: 21h sets the threshold levels of battery supply and junction temperature supervision. this register is reset at a dvdd-por. bit bit name default access bit description 7:5 bvdd_sup 000 r/w sets the threshold (brown-out voltage) at the bvdd input pin f or an interrupt at low battery condition v_brownout=2.74+bvdd_sup*60mv 000: 2.74v 0 01: 2.80v ? 110: 3.10v 111: 3.16v 4:0 jtemp_sup 00000 r/w sets the threshold for junction temperature emergency sh utdown and junction temperature interrupt invoke shutdown at: jtemp_sd=140-jtemp_sup*5 c invoke interrupt at: jtemp_irq=120-jtemp_sup*5 c table 85 charger register name base default charger 2-wire serial 00h charger control register offset: 22h sets the charging current, end of charge voltage and battery temp. supervision. this register is reset at a dvdd-por. bit bit name default access bit description 7 bat_temp_off 0 r/w 0: enables 15ua supply for external 100k ntc resistor 1: disables supply 6:4 chg_i 000 r/w set maximum charging current 111: 400 ma 110: 350 ma 101: 300 ma 100: 250 ma 011: 200 ma 010: 150 ma 001: 100 ma 000: 50 ma 3:1 chg_v 000 r/w set maximum charger voltage in 50mv steps 111: 4.25 v 110: 4.2 v .. 001: 3.95 v 000: 3.9 v 0 chg_off 0 r/w 0: enables charger 1: disables charger revision 1v3 81 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 86 first interrupt register name base default irq_enrd_0 2-wire serial 00h first interrupt register offset: 23h please be aware that writing to this register will enable/disable the corresponding i nterrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description cvdd2_en_sd 0 w invokes shut-down of afe when a ?10% under-voltage spike at cvdd2 occurs 0: disable 1: enable 7 cvdd2_under x r this bit is set when a ?5% under-voltage at cvdd1 occurs cvdd2_en_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd2 0: disable 1: enable 6 cvdd2_over x r this bit is set when a +8% over-voltage at cvdd1 occurs cvdd1_en_sd 0 w invokes shut-down of afe when a ?10% under-voltage spike at cvdd1 occurs 0: disable 1: enable 5 cvdd1_under x r this bit is set when a ?5% under-voltage at cvdd1 occurs cvdd1_en_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd1 0: disable 1: enable 4 cvdd1_over x r this bit is set when a +8% over-voltage at cvdd1 occurs pvdd2_en_sd 0 w invokes shut-down of afe when a ?10% under-voltage spike at pvdd 2 occurs 0: disable 1: enable 3 pvdd2_under x r this bit is set when a ?5% under-voltage at pvdd2 occurs pvdd2_en_irq 0 w enables interrupt for over-voltage/under-voltage supervision of pvdd 2 0: disable 1: enable 2 pvdd2_over x r this bit is set when a +5% over-voltage at pvdd2 occurs pvdd1_en_sd 0 w invokes shut-down of afe when a ?10% under-voltage spike at pvdd 1 occurs 0: disable 1: enable 1 pvdd1_under x r this bit is set when a ?5% under-voltage at pvdd1 occurs pvdd1_en_irq 0 w enables interrupt for over-voltage/under-voltage supervision of pvdd 1 0: disable 1: enable 0 pvdd1_over x r this bit is set when a +5% over-voltage at pvdd1 occurs revision 1v3 82 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 87 second interrupt register name base default irq_enrd_1 2-wire serial 00h second interrupt register offset: 24h please be aware that writing to this register will enable/disable the corresponding i nterrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description 7 sd_time 0 r/w control bit which sets the emergency shut-down time from 5. 4sec to 10.9sec. the shut-down of as3517 is invoked by a high signal at the pwrup input pin. 0: 5.4sec 1: 10.9sec 6 0 n/a 0 w enables interrupt which is invoked whenever a high signal at t he pwrup input pin occurs 0: disable 1: enable 5 pwrup_irq x r this bit is set whenever a high level of min. bvdd/3 at the pwrup i nput pin occurs (pwrup pin is commonly connected to the power-up button) 0 w enables interrupt which is invoked whenever a wake-up from rtc wa ke-up counter occurs 0: disable 1: enable 4 wakeup_irq x r this bit is set when a wake-up has been invoked by the rtc wa ke-up counter. 0 w enables interrupt which is invoked by reaching a voltage t hreshold at mic2 input (voice activation) 0: disable 1: enable 3 voxm2_irq x r this bit is set when a voltage threshold of 5mv rms (unfiltered) at mic2 has been reached (voice activation) 0 w enables interrupt which is invoked by reaching a voltage t hreshold at mic1 input (voice activation) 0: disable 1: enable 2 voxm1_irq x r this bit is set when a voltage threshold of 5mv rms (unfiltered) at mic1 has been reached (voice activation) cvdd3_en_sd 0 w invokes shut-down of afe when a ?10% under-voltage spike at cvdd2 occurs 0: disable 1: enable 1 cvdd3_under x r this bit is set when a ?5% under-voltage at cvdd1 occurs cvdd3_en_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd2 0: disable 1: enable 0 cvdd3_over x r this bit is set when a +8% over-voltage at cvdd1 occurs revision 1v3 83 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 88 third interrupt register name base default irq_enrd_2 2-wire serial 00h third interrupt register offset: 25h please be aware that writing to this register will enable/disable the corresponding i nterrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description 0 w battery over-temperature interrupt setting. 0: disable 1: enable interrupt if battery temperature exceeds 45c the interrupt must not be enabled if the charger block and b attery temperature supervision is disabled 7 battemp_high (level) x r battery over-temperature interrupt reading 0: battery temperature below 45c 1: battery temperature was too high and the charger was t urned off. the charger will be turned on again, when the temperature gets below 42c 0 w battery end of charge interrupt setting 0: disable 1: enable the interrupt must not be enabled if the charger block is dis abled 6 chg_eoc (level) x r battery end of charge interrupt reading 0: battery charging in progress 1: charging is complete, charging current is below 10% of n ominal current, turn off charger to check end of charge again the charger has to be turned on. 5 chg_status x r 0: no charger input source connected 1: charger input source connected, also valid if charger is co nnected during wakeup 0 w charger input status change interrupt setting 0: disable 1: enables an interrupt on a low to high or high to low change o f chgin pin. 4 chg_changed (status change) x r charger input status change interrupt reading 0: charger input status not changed 1: charger input status changed, check chg_status 3 usb_status x r 0: no usb input connected 1: usb input connected, also valid if usb is connected during wa keup. the threshold can be set in the usb_util register (1ah) 0 w usb input status change interrupt setting 0: disable 1: enables an interrupt on a low to high or high to low change o f vbus pin. the threshold can be set in the usb_util register (1ah) 2 usb_changed (status change) x r usb input status change interrupt reading 0: usb input status not changed 1: usb input status changed, check usb_status revision 1v3 84 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com name base default irq_enrd_2 2-wire serial 00h third interrupt register offset: 25h please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description 0 w real time clock supply (rvdd) under-voltage interrupt setting 0: disable 1: enable 1 rvdd_low (level) x r real time clock supply interrupt reading 0: rtc supply o.k. 1: rtc supply (rvdd) was lo w, rtc not longer valid the interrupt gets set in hibernation or during power-up even if t he interrupt is not enabled thus allowing to recognise a change of the battery connected to bvddr during hibernation or shutdown. for a valid reading, the interrupt has to be enabled first. 0 w bvdd under-voltage supervisor interrupt setting 0: disable 1: enable 0 bvdd_low (level) x r bvdd supervisor interrupt setting 0: bvdd is above brown out level 1: bvdd has reached brown out level the threshold can be set in the supervisor register (24h) revision 1v3 85 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 89 fourth interrupt register name base default irq_enrd_3 2-wire serial 0x00 fourth interrupt register offset: 26h please be aware that writing to this register will enable/disable the corresponding i nterrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description 0 w supervisor junction over-temperature interrupt setting 0: disable 1: enable 7 jtemp_high (level) x r supervisor junction over-temperature interrupt reading 0: chip temperature below threshold 1: chip temperature has reached the threshold the threshold can be set in the supervisor register (21h) 6 0 n/a 0 w headphone over-current interrupt setting 0: disable 1: enable the interrupt must not be enabled if the headphone block is dis abled 5 hph_ovc (level) x r headphone over-current interrupt reading 0: no over-current detected 1: headphone over-current detected, headphone amplifier was sh ut down. the current thresholds are 150ma at hpr / hpl pin or 300ma at hpcm pin. the shut-down time can be set in hph_out_r register (0x02) 4 i2s_status x r 0: no lrck on i2s interface detected 1: lrck on i2s interface present 0 w i2s input status change interrupt setting 0: disable 1: enable 3 i2s_changed (status change) x r i2s input status change interrupt reading 0: i2s input status not changed 1: i2s input status changed, check i2s_status 0 w microphone 2 connect detection interrupt setting 0: disable 1: enable 2 mic2_connect (level) x r microphone 2 connect detection interrupt reading 0: no microphone connected to mic input 1: microphone connected at mic input. this interrupt is only invoked when the microphone stage is p owered down. the irq will be released after enabling the microphone stage. detecting a microphone during operation has to be done by m easuring the supply current. 0 w microphone 1 connect detection interrupt setting 0: disable 1: enable 1 mic1_connect (level) x r microphone 1 connect detection interrupt reading 0: no microphone connected to mic input 1: microphone connected at mic input. this interrupt is only invoked when the microphone stage is p owered down. the irq will be released after enabling the microphone stage. detecting a microphone during operation has to be done by m easuring the supply current. revision 1v3 86 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com name base default irq_enrd_3 2-wire serial 0x00 fourth interrupt register offset: 26h please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description 0 w headphone connect detection interrupt setting 0: disable 1: enable 0 hph_connect (level) x r headphone connect detection interrupt reading 0: no headphone connected 1: headphone connected this interrupt is only invoked when the headphone stage is p owered down. the irq will be released after enabling the headphone stage. detecting a headphone during operation is not possible. revision 1v3 87 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 90 fifth interupt register name base default irq_enrd_4 2-wire serial 0x00 fifth interrupt register offset: 27h please be aware that writing to this register will enable/disable the corresponding i nterrupts, while with reading you get the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a dvdd-por. bit bit name default access bit description 7:6 t_deb<1:0> 00 r/w sets the usb and charger connect de-bounce time: 00: 340ms 01: 170ms 10: 85ms 11: 4ms 5 xirq_ah 0 r/w sets the active output state of the xirq line: 0: irq is active low 1: irq is active high 4 xirq_pp 0 r/w sets the xirq output buffer type: 0: irq output is open drain 1: irq output is push pull 0 w microphone 2 remote key press detection interrupt setting 0: disable 1: enable 3 rem2_det (edge) x r microphone 2 remote key press detection interrupt reading 0: no key press detected 1: microphone 2 supply current got increased, remote key p ress detected -> measure mics supply current 0 w microphone 1 remote key press detection interrupt setting 0: disable 1: enable 2 rem1_det (edge) x r microphone 1 remote key press detection interrupt reading 0: no key press detected 1: microphone 1 supply current got increased, remote key p ress detected -> measure mics supply current 0 w rtc timer interrupt setting 0: disable 1: enable 1 rtc_update (edge) x r rtc timer interrupt reading 0: no rtc interrupt occurred 1: rtc timer interrupt occurred. selecting minute or second i nterrupt can be done via rtct register (29h) 0 w adc end of conversion interrupt setting 0: disable 1: enable 0 adc_eoc (edge) x r adc end of conversion interrupt reading 0: adc conversion not finished 1: adc conversion finished. read out adc_0 and adc_1 reg ister to get the result (2eh & 2fh) revision 1v3 88 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 91 rtcv register name base default rtcv 2-wire serial 23h rtc voltage register offset: 28h this register is reset at a dvdd-por. bit bit name default access bit description 7:4 v_rvdd 0010 r/w selects the rvdd output voltage level (1v to 2.5v) default: 1. 2v rvdd= 1v + v_rvdd*0.1v 3:2 1 rtc_on 1 r/w rtc counter clock control: 0: disable clock for rtc counter 1: enables clock for rtc counter 0 osc32_on 1 r/w switches the 32khz oscillator on a 32khz watch crystal need t o be connected to pins xin32/xout32 0: disable 32khz oscillator 1: enables 32khz oscillator table 92 rtcv register name base default rtct 2-wire serial 40h rtc timing register offset: 29h this register is reset at a rvdd-por. bit bit name default access bit description 7 irq_min 0 r/w 0: generates an interrupt every second 1: generates an interrupt every minute the interrupt has to be enable in irq_enrd_4 (27h) 6:0 rtc_tbc<6:0> 1000000 r/w these bits are used to correct the inaccuracy of the used 3 2khz crystal. trimming register for rtc, 128 steps @ 7.6ppm 000000: 1 (7.6ppm) 000001: 2 (15.2ppm) ? 100000: 64 (488ppm) ? 111110: 126 (960.8ppm) 111111: 127 (968.4ppm) table 93 rtc_0 to rtc_3 register name base default rtc_0 to rtc_3 2-wire serial 00 00 00 00h rtc time-base seconds register offset: 2ah to 2dh this register is reset at a rvdd-por. adr. byte name default access bit description 2ah rtc_0 00h r/w qrtc<7:0>; rtc seconds bits 0 to 7 2bh rtc_1 00h r/w qrtc<15:8>; rtc seconds bits 8 to 15 2ch rtc_2 00h r/w qrtc<23:9>; rtc seconds bits 9 to 23 2dh rtc_3 00h r/w qrtc<31:24>; rtc seconds bits 24 to 31 revision 1v3 89 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com table 94 adc_0 register name base default adc_0 2-wire serial 0000 00xx first 10-bit adc register offset: 2eh writing to this register will start the measurement of the selected source. this register is reset at a dvdd-por, exception are bit 8 and 9. bit bit name default access bit description 7:4 adc_source 00000000 r/w selects adc input source 0000: chgout 0001: bvddr 0010: defined by dc_test in register 0x18 0011: chgin 0100: vbus 0101: battemp 0110: mic1s 0111: mic2s 1000: vbe_1ua 1001: vbe_2ua 1010: i_mic1s 1011: i_mic1s 1100: rvdd 1101: reserved 1110: reserved 1101: reserved 3:2 00 n/a 1:0 adc<9:8> xx r/w adc result bit 9 to 8 table 95 adc_1 register name base default adc_1 2-wire serial xxxx xxxx second 10-bit adc register offset: 2fh this register is not reset. bit bit name default access bit description 7:0 adc<7:0> xxxx xxxx r/w adc result bit 7 to 0 table 96 uid_0 to uid_7 register name base default uid_0 to uid_7 2-wire serial n/a unique id register offset: 38h to 3fh this register is read only and is not reset. adr. byte name default access bit description 38h uid_0 n/a r unique id byte 0 39h uid_1 n/a r unique id byte 1 3ah uid_2 n/a r unique id byte 2 3bh uid_3 n/a r unique id byte 3 3ch uid_4 n/a r unique id byte 4 3dh uid_5 n/a r unique id byte 5 3eh uid_6 n/a r unique id byte 6 3fh uid_7 n/a r unique id byte 7 revision 1v3 90 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 10 typical application figure 32 typical application schematic 1 revision 1v3 91 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com figure 33 typical application schematic 2 revision 1v3 92 - 93 ams ag technical content still valid
as3517 v17 data sheet, confidential ? 2003-2007, austriamicrosystems ag, 8141 unterprems taetten, austria-europe. all rights reserved. www.austriamicrosystems.com 11 copyright copyright ? 2008, austriamicrosystems ag, schloss premstaetten, 8141 unterpremstaetten, austria-europe. trademarks registered ? . all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks of their respective companies. 12 disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent identification provisions appearing in its term o f sale. austriamicrosystems ag makes no warranty, ex press, statutory, implied, or by descrip tion regarding the information set forth he rein or regarding the freedom of the described device s from patent infringement. austriamicrosystems ag rese rves the right to change specifications and prices at any time and without notice. therefore, prior to designing this pr oduct into a system, it is neces sary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial applications. applic ations requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, m edical life- support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag f or each application. the information furnished here by austriamicrosystems ag is belie ve d to be correct and accurate. however, austriamicrosystems a g shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in conne ction with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. 13 contact information headquarters: austriamicrosystems ag business unit c ommunications a 8141 schloss premst?tten, austria t. +43 (0) 3136 500 0 f. +43 (0) 3136 5692 info@austriamicrosystems.com for sales offices, distributors and representatives, please visit: www.austriamicrosystems.com revision 1v3 93 - 93 ams ag technical content still valid

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